Advanced FPGA Based System Design

Advanced FPGA Based System Design Lecture-6 & 7 VHDL Data Types By: Dr Imtiaz Hussain imtiaz.hussain@faculty.muet.edu.pk

Contents • Data Types • Bit & Bit Vectors • Std_Logic and std_logic_vectors • Std_Ulogicand std_Ulogic_vectors • Arrays • 1D, 2D, 1DX1D • Records • Signed & Unsigned • Data Conversion

Data Types • VHDL contains a series of pre-defined data types, specified through the IEEE 1076 and IEEE 1164 standards. • Data type definitions can be found in the following packages / libraries: • Package standard of library std: Defines BIT, BOOLEAN, INTEGER, and REAL data types. • Package std_logic_1164 of library ieee: Defines STD_LOGIC and STD_ULOGIC data types.

Data Types • Package std_logic_arith of library ieee: Defines SIGNED and UNSIGNED data types, plus several data conversion functions, like conv_integer(p), conv_unsigned(p, b), conv_signed(p, b), and conv_std_logic_vector(p, b). • Packages std_logic_signed and std_logic_unsigned of library ieee: Contain functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type SIGNED or UNSIGNED, respectively.

Data Types • BIT & BIT_VECTORS (2-Level Logic ‘0’ and ‘1’)

Data Types • To assign a value to a signal ‘<=’ must be used

Examples of BIT and BIT_VECTORS • Initialize a variable ‘var1’ with binary value ‘1’. • Initialize an 8-bit variable ‘var2’ with MSB=‘1’ and LSB= ‘0’ and all the values in between equal to 1. • var3=10000100 • var4=1000100 MSB MSB

Data Types • STD_LOGIC and STD_LOGIC_VECTOR (8 value system)

Data Types • STD_LOGIC and STD_LOGIC_VECTOR

Data Types • STD_ULOGIC and STD_ULOGIC_VECTO R (9-Level Logic system). • STD_LOGIC is therefore defined as subtype of STD_ULOGIC.

Examples of Data Types

Data Types(Legal and Illegal operation B/W data of different types)

Arrays • Arrays are collection of objects of same type. • They can be one-dimensional (1D), two-dimensional (2D), or one-dimensional-by-one-dimensional (1Dx1D). An array of vectors (1Dx1D array) A single value (scalar) An array of scalars (2D array) A vector (1D array)

Arrays • To Specify a new array type • To make use of new array type

Arrays (Example of 1Dx1D array) • Say that we want to build an array containing four vectors, each of size eight bits. • Let us call each vector by row, and the complete array by matrix • Additionally, say that we want the leftmost bit of each vector to be its MSB (most significant bit), and that we want the top row to be row 0. Then the array implementation would be the following. row (7 down 0) Matrix (0 to 3)

Arrays (Example of 1Dx1D array) row (7 down 0) • Another way x=Matrix (0 to 3)

Arrays (Example of 2D array) • Array below is a 2D array

Arrays • Array Initialization TYPE myarray IS ARRAY (3 DOWN 0) OF STD_LOGIC:=“0001”;

Example • Write the syntax of following arrays (a) (c) (b) (d)

Examples • Write syntax for following • (A) • (B) • (C) • (d)

Examples (legal and illegal assignments)

Examples (legal and illegal assignments) row array1

Examples (legal and illegal assignments) array2 array3

Examples (legal and illegal assignments)

Records • Records are similar to arrays, with the only difference that they contain objects of different types.

Signed & Unsigned Data Types • These types are defined in the std_logic_arith package of the ieeelibrary. • SIGNED and UNSIGNED data types are intended mainly for arithmetic operations. • Their syntax is illustrated in the examples below.

Signed & Unsigned Data Types • An UNSIGNED value is a number never lower than zero. • For example, ‘‘0101’’ represents the decimal 5, while ‘‘1101’’ signifies 13. • If type SIGNED is used instead, the value can be positive or negative (in two’s complement format). • Therefore, ‘‘0101’’ would represent the decimal 5, while ‘‘1101’’ would mean -3. • Logical operations are not allowed but there are no restrictions to relational (comparison) operations.

Legal/illegal operations with Signed & Unsigned Data Types

Legal/illegal operations with std_logic_vector

Data Conversion • VHDL does not allow direct operations (arithmetic, logical, etc.) between data of different types. • Therefore, it is often necessary to convert data from one type to another. • This can be done in basically two ways: • write a piece of VHDL code • invoke a FUNCTION from a pre-defined PACKAGE which is capable of doing it for us.

Data Conversion • If the data are closely related (that is, both operands have the same base type, despite being declared as belonging to two different type classes), then the std_logic_1164of the ieee library provides straightforward conversion functions.

Data Conversion • Several data conversion functions can be found in the std_logic_arith package of the ieee library. They are: • conv_integer(p) : Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an INTEGER value. • conv_unsigned(p, b): Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGICto an UNSIGNED value with size b bits. • conv_signed(p, b): Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to a SIGNED value with size b bits. • conv_std_logic_vector(p, b): Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or STD_LOGIC to a STD_LOGIC_VECTOR value with size bbits.

Example Data Conversion

The Fundamental Synthesizable VHDL data types

Examples • Single bit vs. Bit vector

Examples • Figure shows the top-level diagram of a 4-bit adder. The circuit has two inputs (a, b) and one output (sum). A(3:0)  Sum(4:0) B(3:0)

Problems • The problems below are based on the following TYPE definitions and SIGNAL declarations:

Problems • Problem#1: • Determine the dimensionality (scalar, 1D, 2D, or 1Dx1D) of the signals given. Also, write down a numeric example for each signal. • Problem#2: • Determine which among the assignments in table (available in class) are legal and which are illegal. Briefly justify your answers. Also, determine the dimensionality of each assignment (on both sides).

Advanced FPGA Based System Design