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SOI-Enabled 3D Integrated Circuit Technology TIPP 2011 14 June 2011

SOI-Enabled 3D Integrated Circuit Technology TIPP 2011 14 June 2011. C.K. Chen , B Wheeler, D.R.W. Yost, J.M. Knecht, and C.L. Keast MIT Lincoln Laboratory.

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SOI-Enabled 3D Integrated Circuit Technology TIPP 2011 14 June 2011

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  1. SOI-Enabled 3D Integrated Circuit Technology TIPP 2011 14 June 2011 C.K. Chen, B Wheeler, D.R.W. Yost, J.M. Knecht, and C.L. Keast MIT Lincoln Laboratory *This work was sponsored by the Defense Advanced Research Projects Agency under Air Force contract #FA8721-05-C0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government .

  2. Why 3D? Exploiting Different Process Technologies High Performance m-Processors Density, Speed, & Power 3DIC Cross Section Mixed Material Integration Compound Semiconductors Advanced Focal Plane Imagers 100% Fill Factor

  3. Improve Density by Chip Stacking Stacked-Die Wire Bonding Stacked Chip-Scale Packages 1 mm ChipPAC, Inc. Tessera, Inc.

  4. Approaches to High-Density 3D Integration(Photos Shown with Same Scale) 10 mm 10 mm 10 mm 3D-Vias 3D-Vias Tier-3 Tier-2 Tier-1 Thru silicon via (TSV) for interconnecting circuit layers through thinned bulk Si layers TSMC 30-mm pitch, 2010 IEDM Micro bump bond for flip-chip interconnecting two circuit layers TSMC 40-mm pitch, 2010 IEDM MITLL SOI-based 3D vias for interconnecting three circuit layers

  5. Outline • Motivation • Lincoln’s 3D Integrated Circuit Process • 3D Circuit Demonstrations • Summary

  6. 2D versus 3D Circuits Handle Silicon Tier 2 Tier 3 Metal Deposited Oxide Handle Silicon Buried Oxide Silicon Single Circuit Layer 2D Integrated Circuit Cross-Section Circuit Layers 3D Vias Tier 1 3D Integrated Circuit Cross-Section

  7. 3D Integrated Circuit Process Flow Buried Oxide Tier-3 Handle Silicon Buried Oxide Tier-2 Handle Silicon Metal Deposited Oxide Buried Oxide Buried Oxide Handle Silicon Tier-1 Silicon • Fabricate circuits on Silicon-on-Insulator (SOI) wafers (active Si layer is separated from a handle bulk Si substrate by an insulating buried oxide) • Assemble circuit layers into a 3D stack Tier-1 can be either Bulk or SOI

  8. Tier2-to-Tier1 Alignment and Bonding Handle Silicon Tier-2 Buried Oxide Metal Deposited Oxide Buried Oxide Buried Oxide Handle Silicon Tier-1 Silicon

  9. Tier2 Substrate Removal andElectrical Connection to Tier1 Buried Oxide Handle Silicon Tier-1 Handle Silicon Tier-2 Buried Oxide Tungsten Metal Deposited Oxide Buried Oxide Silicon

  10. Tier3 Bonding and Alignment Buried Oxide Tier-3 Handle Silicon Buried Oxide Handle Silicon Tier-1 Tungsten Metal Deposited Oxide Buried Oxide Silicon

  11. Tier3 Substrate Removal andElectrical Connection to Tier1-Tier2 Handle Silicon Tier-3 Buried Oxide Buried Oxide Handle Silicon Tier-1 Tungsten Metal Deposited Oxide Buried Oxide Silicon • SOI enables elimination of tier2 & tier3 handle Si wafer • Thru Si via (TSV) becomes thru oxide via (TOV) • TOV offers many advantages vs. TSV – more compact, higher density, oxide isolation, reduced parasitics 150-mm-diameter three-tier wafer

  12. 3D Enabling Technologies • Precision wafer aligner-bonder • Designed and built at MITLL • Incorporates IR cameras • Demonstrated 0.25-mm wafer-to-wafer alignment capability • Low temperature oxide-oxide bonding • Allows use of standard IC processing to complete 3D integration • Room temperature bond followed by a 175C post-bond anneal • Concentric 3D via • Formed by high-density-plasma oxide etch • Interconnect formed by CVD tungsten deposition 3D Via Chain SEM cross section

  13. Design Rule 3D Vias(SEM Images Shown at Same Scale with Drawn 3D Via Size) oxide bond epoxy bond 10um ~15 mm 2000 2 mm 2004 1.75 mm 2005 1.25 mm 2008 1.00 mm current • Key 3D Via Developments • Replaced epoxy with oxide bond allowing use of standard silicon integrated circuit processing • Developed concentric 3D vias, allowing much higher density • Reduced 3D via size • Reduced active area exclusion 64 x 64, 50-mm pixel LADAR 3rd 3D multi project run InP detector array 1024×1024, 8-μm pixel visible image sensor 64 x 64, 12-μm active-pixel sensor

  14. 3-Tier 3DIC Cross-SectionDARPA 3DM3 Multiproject Run Oxide Bond Interface 20 mm Three FDSOI CMOS Tiers Transistor Layers RF Back Metal Tier-3 3D Via 3D Via Tier-2 Tier-1 Tier-1 Transistor Layer Tier-3 RF tungsten gate shunt Tier-3 2-mm-thick RF back metal 3DIC Process Highlights 11 metal interconnect levels 1.25-mm 3D via tier interconnect Stacked 3D vias allowed

  15. Transistor CharacteristicsBefore and After 3D Integration • Ids-Vgs plots • Width/Length = 8/0.15 mm • Vdd = +/-1.5V for p/nMOS • Before ( ) & after ( ) 3D integration • No significant change before and after 3D integration ▬ + Tier 2 Tier 1 Tier 3

  16. Outline • Motivation • Lincoln’s 3D Integrated Circuit Process • 3D Circuit Demonstrations • Summary

  17. 3D Circuit Demonstrations • Advanced Focal Plane Imager (ISSCC 2005 & 2009) • Photoactive and readout circuit layers • 100% fill factor • 1024 x 1024 pixel array • 8-mm pixel pitch • 3-Tier Laser Radar Focal Plane (ISSCC 2006) • 3D Integration of three different process technologies • 1.5 V FDSOI CMOS counter circuit layer • 3.3 V APD drive-sense circuit layer • 30 V avalanche photodiode layer • High Speed 10Gb/s Tier-to-Tier Interconnect (Frank Chang, UCLA, ISSCC 2007 ) Image from 3D Chip 3-Tier Pixel Layout RFI Test @ 12.5 GHz Output Eye diagram

  18. Mixed Material 3D IntegrationInGaAs Diode Array with SOI CMOS Readout 150 mm 3D Integrated SOI / InP Wafer SEM Cross Section of Pixel Array • Established 3D Si-compatible III-V process • Demonstrated 6-mm-pixel SWIR focal plane 6 mm Top metal FET SOI 3D TOV M2 M3 Oxide p InP InP InGaAs n InP

  19. Enabling 3D Design Multiproject Fabrication Runs • Funded by DARPA to explore new 3D circuit applications • Engage government, academic, and industry design groups in a Multiproject run, using a proven 3D integration process • Provided 3D process design kit based on a decade of fabrication experience over ten different designs • Third 3D Multiproject statistics: • 38 design proposals received • Requested area: 760 mm2 • Available area: 484 mm2 3D Multiproject Floorplan UFL RPI DOD Eutecus Vanderbilt Cornell U Pitt UMN JHU NCSU U Idaho UNH JHU PSU Rochester UNH ASU ASU MITLL MITLL MITLL NCSU Yale Sensing Mach PSU Wash StL UNH-MIT NRL-Cornell Fermi Lab

  20. Third 3D IC Multiproject Run (3DM3)(Three Tiers of 150-nm 1.5-volt FDSOI CMOS) Completed 3DM3 Die photo 22 mm 3DM3 Participants(Industry, Universities, Laboratories) ASU Cornell DoD Eutecus Fermi Nat’l Lab IBM Johns Hopkins MIT (Campus) MIT Lincoln Lab NCSU NRL Penn State RPI Sensing Mach. SUNY UNH U Idaho U Florida U Minnesota U Pittsburgh U Rochester U Tenn Vanderbilt Wash U StL Yale • First 3D Multiproject run 3DL1 • chips delivered April 2006 • Second 3D Multiproject run 3DM2 • chips delivered Nov 2007 • Third 3D Multiproject run 3DM3 • chips delivered Aug 2010 3D Circuits Secure ID/Anti-tamper, Stacked SRAM & DRAM, Stacked microprocessor, Hi-speed transmit/ receive, One-chip GPS, Network-on-chip, Reconfigurable neural network, SAR processor elements, RF-switching power converter, Power management for 3DIC’s, Integrated RF MEMS, Implantable biosensors, Bio lab-on-chip 3D Imaging Applications ILC pixel readout, low-power pattern recognition 3D vision chip, Multi-core processor with image recognition, Focal plane image processor, Sub-l-sized pixel imaging array 3D Technology Characterization 3D radiation test structures, Jitter-clock skew-propagation delay, Hi-speed I/O, RF building blocks, Meta-material inductor, Stacked MOSFET

  21. 3D Integrated Foundry Wafers Foundry Wafer Die Photo 3D integrated Jazz wafers • Demonstrated bonding and 3D integration of metal-only Jazz wafers • Achieved 100% yield of design-rule 10K 3D via chains 22 mm 150 mm

  22. Summary • SOI-Enabled 3DIC Process • Process characterization • TOV (thru oxide via) vs. TSV (thru silicon via) smaller, higher density, reduced parasitics • 3D Circuit Demonstrations • Advanced Focal Planes (100% fill factor) • 3D LADAR Chip (mixed technologies) • High Speed 10 Gbps Interconnect • InP-Si Integration (mixed materials) • 3D Multiproject Designs • 3D Integration of Foundry Wafers

  23. Supplemental Slides

  24. Back Metal-to-Transistor ContactUse of Back Via Improves Design Flexibility Nominal Cross Section • Nominal design rule transistor layout • Required layers -- contact (CON), metal-1 (M1), back via (BV), & back metal (BM1) Transistor • Experimental back via-transistor layout • Required layers – back via (BV) & back metal (BM1) • More compact layout reduces transistor footprint by ~40% • Allows back metal use as local interconnect routing layer Experimental BV Cross Section Transistor

  25. Transistor CharacteristicsExperimental Back Via vs. Nominal Layout • Ids-Vgs and Ids-Vds plots • Width/Length = 8/0.15 mm • Vdd = +/-1.5V for p/nMOS Tier 3 Vg = 0 to -1.5 V in 0.25 V steps Vg = 0 to 1.5 V in 0.25 V steps

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