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Set Reference

Structure of BER block in TELL1. GOL_data. Counter. Compare. Error pulses. Set Reference. The implementation. The VHDL code for BER_check(1). set_reference:process(clk,reset) begin if reset = '1' then next_reference <= X"0000"; elsif rising_edge(clk) then

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Set Reference

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  1. Structure of BER block in TELL1 GOL_data Counter Compare Error pulses Set Reference

  2. The implementation

  3. The VHDL code for BER_check(1) set_reference:process(clk,reset) begin if reset = '1' then next_reference <= X"0000"; elsif rising_edge(clk) then ----set the reference for next word if dv = '1' then next_reference <= indata + 1; end if; end if; end process; Process1: set the reference for the next word based on current word. There is no internal running counter used as reference.

  4. The VHDL code for BER_check(2) compare: process(clk,reset) begin if reset = '1' then not_equal <= '0'; not_equal_l <= '0'; not_equal_ll<= '0'; dv_l <= '0'; elsif rising_edge(clk) then dv_l <= dv; not_equal <= '0'; not_equal_l <= not_equal; not_equal_ll<= not_equal_l; --Skip the first word because -- the reference is not set yet if (dv = '1' and dv_l = '1') then if(indata /= next_reference) then not_equal <= '1'; end if; end if; end if; end process; Process2: To compare the received word with the reference. Set not_equal signal accordingly. The first word after the setting of GOL DataValid must be skipped because the correspond reference is not available at that time.

  5. The VHDL code for BER_check(3) Process3: To decode error types. If only one bit is reverted in word(n). Then word(n) != word(n-1)+1 word(n+1) != word(n)+1 Thus two consecutive mismatch occur, we call this as “BER_error” If there is word lost. For example we lost 0x3456 as below: .. 0x3454,0x3455,[lost],0x3457,0x3458… Then 0x3455 == 0x3454 + 1 0x3457 != 0x3455 + 1 0x3458 == 0x3457 + 1 There is ONLY one single mismatch, we call this as “WORD_missing”. gen_error_signal: process(clk,reset) begin if reset = '1' then BER_error <= '0'; WORD_missing <= '0'; elsif rising_edge(clk) then BER_error <= '0'; WORD_missing <= '0'; --two consecutive mismatch, bit error occurs if not_equal = '1' and not_equal_l = '1' then BER_error <= not BER_error; end if; --Only one single mismatch. The counter jumps if not_equal = '0' and not_equal_l = '1' and not_equal_ll = '0' then WORD_missing <= '1'; end if; end if; end process;

  6. counter: process(clk,reset) begin if reset = '1' or BER_reset = '1' then dv_l <= '0'; BER_cnt <= (others => '0'); BER_rcv_cnt <= (others => '0'); WME_cnt <= (others => '0'); elsif rising_edge(clk) then dv_l <= dv_en; -- if dv_en = '1' and dv_l = '1' then BER_rcv_cnt <= BER_rcv_cnt + 1; end if; -- if BER_error = '1' then if BER_cnt /= X"FFFFFF" then BER_cnt <= BER_cnt + 1; end if; end if; -- if WORD_missing = '1' then if WME_cnt /= X"FF" then WME_cnt <= WME_cnt + 1; end if; end if; end if; end process; The VHDL code for BER_counter Simple counters, Note: 1: the error_counter should not overflow. 2: the BER_reset should be implemented as asynchronies reset to guarantee it still works even the correspond “clk” in not active (this happens if the optical cable in not plugged)

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