Energy optimization for probabilistic boolean logic circuits and its applications

Energy optimization for probabilistic boolean logic circuits and its applications Presenter: Yung-Chun Hu Advisor: Prof. Chun-Yao Wang 2014/06/16

Outline • Introduction • Problem Formulation • Power Optimization • Applications • Experimental Results • Conclusion

Probabilistic CMOS Noise effect Lower VDD

Energy of a Probabilistic Inverter Energy per switching: Energy ratio Probability

Probabilistic Boolean logic • Notations • OR: • AND: • NOT: • Let probabilistic parameter A 0.9 F B

Voltage v.s. probability • PTM 45nm SPICE model INV NAND2

Correctness Definition • Correctness under an input pattern • Golden value = 1： • Golden value = 0： • Correctness of POj：

Problem formulation • Problem formulation: • Given: • A Boolean circuit • A library of probabilistic gates • Correctnessconstraint • Determine: The locations of probabilistic gates such that power consumption minimized

Random vs. Level-order replacement

testability • A Statistic-based approach to testability analysis,C.-C. Chiou et al, 2008 • Notations: • V(wire/gate): simulation results on a wire/gate • Cr(wire/gate): criticality vector on a wire/gate • The change of critical bits will cause at least one PO change.

Testability

Testability 0.25 1 0.5 1 1 0.5

Testability 0.25 1 1 0.5 4 1 2 5 1 0.5 6 3

PO-aware Testability

PO-aware Testability 0.083 0.33 0.25 0.33 0.33 0.167

PO-aware Testability 0.083 1 0.33 4 0.25 3 0.33 5 0.33 0.167 6 2

Po-aware testability • # of probabilistic gates=2, p=0.9 • Since we build the criticality vectors for each PO, the weighted PO-aware testability can be obtained through the following equation:

PO-aware Testability-based replacement approach

Applications • Three applications • 32-bit adder • Average image filter • Edge detector • Weighted correctness and testability evaluation: for ith bit

adder • AVG_Weighed_Correctness=99

adder • Error & Power

Average image filter • An average image filter can be used to soften an image. • For every pixel, the filter averages its surround 8 pixels and itself.

Average image filter • Resultant images and PSNR values

Average image filter • AVG_Weighed_Correctnessv.s. PSNR value

Average image filter • AVG_Weighed_Correctnessv.s. power

Average image filter • AVG_Weighed_Correctnessv.s. normalized power Around 20% power reduction

Edge detector • Sobel operation: , where A is the source image and is convolution operation • Approximation:

Edge detector • The difference between Sobel operation and approximation • PSNR: 47.67

Edge detector • Resultant images and PSNR values

Edge detector • AVG_Weighed_Correctnessv.s. PSNR value

Edge detector • AVG_Weighed_Correctnessv.s. power

Edge detector • AVG_Weighed_Correctnessv.s. normalized power Around 10% power reduction

Experimental results • The relationship between switching energy consumption and correctness under (a) AVG_Correctness for alu4. (b) AVG_Correctness for dalu.

Experimental results • The ratios of probabilistic gates and switching energy consumption in PBCs with voltage domains of 1.0V, 0.9V, or 0.8V under the AVG_Correctness constraint of 90%

Experimental results • The ratio of circuit delay under AVG_Correctness constraint of 90%for 0.8V voltage domain

Experimental results • Probabilistic gate number comparisom between different strategies under AVG_Correctness constraint of 90%for 0.8V voltage domain

Experimental results • Power-delay-product of PO-aware testability-based strategy under AVG_Correctness constraint of 90%for 0.8V voltage domain

Conclusion • This is the first work that discusses the power minimization of PBC designs • We propose a power minimization flow that efficiently reduces the power consumption of PBC designs

Thank you for your attention Q & A

Energy optimization for probabilistic boolean logic circuits and its applications