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Energy Optimization of Probabilistic BooleaN Circuits

Energy Optimization of Probabilistic BooleaN Circuits. Yung-Chun Hu & Ching -Yi Huang & Black 2013/12/02. Outline. Motivation Introduction Problem Formulation Probabilistic gate assignment and selection Optimization: Near-redundant removal Issues Future work. Motivation.

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Energy Optimization of Probabilistic BooleaN Circuits

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  1. Energy Optimization of Probabilistic BooleaN Circuits Yung-Chun Hu & Ching-Yi Huang & Black 2013/12/02

  2. Outline • Motivation • Introduction • Problem Formulation • Probabilistic gate assignment and selection • Optimization: Near-redundant removal • Issues • Future work

  3. Motivation Moore’s Law v.s. power issue

  4. Solutions • Multiple Processors • 3D IC • FinFET • Single Electron Transistor(SET) • Probabilistic CMOS(PCMOS) • …

  5. Probabilistic CMOS Lower Vdd Power Voltage

  6. Problem formulation • Given • A deterministic circuit • Correctness constraint • Derive • An energy optimized probabilistic Boolean circuit

  7. Outline • Motivation • Introduction • Problem Formulation • Probabilistic gate assignment and selection • Optimization: Near-redundant removal • Future work

  8. Probability selection • PTM 45nm bulk • Vtn 0.466 ; Vtp 0.412 • Wn 0.415 ; Wp 0.63; L 0.5 Energy (normalized) Probability

  9. P-gate assignment • Observation • Same input pattern and stuck-at fault, different outputs 1 A X 1 S-A-0 B 1/0 Y 1 F Z 1 C D 1 S-A-0 A X 1 1 B Y 1 F Z 1 C D

  10. P-gate assignment • We usually use testability/observability to measure the difficulty of propagating fault effects to POs • Fault effects caused by probabilistic behavior have greater chance to be blocked if its testability is lower

  11. P-gate assignment Random Testability-order

  12. Outline • Motivation • Introduction • Problem Formulation • Probabilistic gate assignment and selection • Optimization: Near-redundant removal • Future work

  13. Redundant Removal • In deterministic circuit, we can inject SA faults and remove redundant wires. SA fault Observable? No Remove the wire

  14. Redundant Removal • Example The only possible test pattern is (1,1,0) S-A-0 1 A 1 B 0 C F

  15. Redundant Removal • Example The only possible test pattern is (1,1,0) S-A-0 1 A 1 B 0 C 1/0 1 F 1

  16. Redundant Removal • Example 0 0 C 1/0 1 F 1

  17. Near-redundant removal • Regard signals which have high probability to be 0 or 1 as stuck-at-faults E A 0.0375 w 0.9 0.9625 0.3 B 0.075 Correctness=0.99375 0.25 C D Assume input space is a full set, w has probability of 0.9625 to be 1

  18. Near-redundant removal • In PBC, we may regard signals which have high probability to be 0 or 1 as stuck-at-faults. 0 Correctness=0.977 The node reduction is 66%.

  19. Near-redundant removal

  20. Probability selection issue • Number of probability? The more probability we use, the more voltages we need • Realization Power island Power islands in an SoC Power islands in a circuit? 1.0V 1.1V Scale down 0.8V 0.9V

  21. Power Issue P-gate→P-gate General-gate→P-gate power voltage

  22. Power Issue P-gate→General-gate power voltage

  23. Future work • Observability-Probability-Correctness observation

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