Overview slides before midterm exam

1. Overview slides before midterm exam

2. human memory human DNA book encyclopedia 2 hrs CD audio 30 sec HDTV page Evolution in DRAM Chip Capacity 4X growth every 3 years! 0.07 m 0.1 m 0.13 m 0.18-0.25 m 0.35-0.4 m 0.5-0.6 m 0.7-0.8 m 1.0-1.2 m 1.6-2.4 m

3. 100 P6 Pentium ® proc 486 10 Die size (mm) 386 286 8080 8086 ~7% growth per year 8085 8008 ~2X growth in 10 years 4004 1 1970 1980 1990 2000 2010 Year Die Size Growth Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel

4. Clock Frequency Lead microprocessors frequency doubles every 2 years 10000 2X every 2 years 1000 P6 100 Pentium ® proc 486 Frequency (Mhz) 386 10 8085 286 8086 8080 1 8008 4004 0.1 1970 1980 1990 2000 2010 Year Courtesy, Intel

5. Power Dissipation Lead Microprocessors power continues to increase 100 P6 Pentium ® proc 10 486 286 8086 Power (Watts) 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Power delivery and dissipation will be prohibitive Courtesy, Intel

6. 10000 1000 Rocket Nozzle 100 Nuclear Power Density (W/cm2) Reactor 8086 10 4004 P6 Hot Plate 8008 Pentium® proc 8085 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Power Density Courtesy, Intel

13. Why Scaling? • Technology shrinks by ~0.7 per generation • With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly • Cost of a function decreases by 2x • But … • How to design chips with more and more functions? • Design engineering population does not double every two years… • Hence, a need for more efficient design methods • Exploit different levels of abstraction

14. Physical description (layout, circuit, etc.) Simulation for system specification Design Abstraction Levels Behavior description (Verilog, HDL, etc.) Silicon compilation

15. Microscopic issues ultra-high speeds power dissipation and supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability clock distribution Macroscopic issues time-to-market design complexity (millions of gates) high levels of abstractions reuse and IP, portability systems on a chip (SoC) tool interoperability Major Design Challenges

16. Why learn full hierarchy? • somebody has to do it at each level • good design of cell or modules requires in-depth knowledge • stringent constraints • vertical knowledge in horizontally integrated companies • global factors (interconnect for power, ground, clock, bus, etc.) • new issues previously considered not critical: • dynamic power dissipation • interconnect delay and coupling • many other “surprises” waiting ahead!!! • Murphy’s law (when things can go wrong, they do) comes again and again.

17. Course overview: VLSI design • Job of VLSI designer: design a circuit block to meet one or more objectives: • Maximize speed, performance • Minimize power consumption • Minimize area • Noise immunity (robustness) • How? • Choice of circuit style (static, dynamic, etc) • Circuit design, transistor sizing • Interconnect design, efficient layout

19. VLSI Design Stages • Logic Design/Simulation • Partition architecture into cycles / latches • Verify against architecture specification • Circuit Design/Simulation • Transistor sizing • Performance verification • Static Timing Analysis • Verify margin requirements • Physical Design • Draw masks for layout, following design rules • Placement and routing • Parasitic extraction

22. VLSI Design Approaches • Gate Arrays • Prefabricated chips containing transistors/gates and local interconnects • Upper level wires added to implement design • Quick, but sub-optimal • Standard Cells • Cells in a library with fixed height, width • Cells characterized for delay, power • Design is fast – layout mostly automatic • Custom Design • Variable sizes • Extensive checking / verification required • Dense design, best performance Ease of Design Performance

24. Design Rules • Interface between the circuit designer and process engineer • Guidelines for constructing process masks • Unit dimension: minimum line width • scalable design rules: lambda parameter • absolute dimensions: micron rules • Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur • A complete set includes • set of layers • intra-layer: relations between objects in the same layer • inter-layer: relations between objects on different layers  is half of the minimum feature size in a given process (e.g., min. gate length).

25. The Threshold Voltage VT = VT0 + (|-2F + VSB| - |-2F|) where VT0 is the threshold voltage at VSB = 0 and is mostly a function of the manufacturing process • Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc. VSB is the substrate-bias voltage F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is the thermal voltage; NA is the acceptor ion concentration; ni 1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in pure silicon)  = (2qsiNA)/Coxis the body-effect coefficient (impact of changes in VSB) (si=1.053x10-10F/m is the permittivity of silicon; Cox = ox/tox is the gate oxide capacitance with ox=3.5x10-11F/m)

26. MOSFET Current –Voltage Relationships (Non saturation Region) • The region for which VDS< VDS(sat) is known as the nonsaturation region. The ideal current voltage characteristics in this region are describe by the equation iD= Kn[(VGS-VTN)VDS-VDS2/2] Where the parameter Kn is called the conduction parameter or gain factor for the n-channel device and is given by Kn= nCoxW/L Where Cox is the oxide capacitance per unit area. The capacitance is given by Cox= ox/tox Where tox is the oxide thickness and ox is the oxide permittivity. The parameter n is the mobility of the electron in the inversion layer.

27. MOSFET Current –Voltage Relationships (Saturation Mode) • In saturation mode VDS ≥ VGS-Vt . The expression for saturation mode can be obtained by substituting VDS = VGS-Vt resulting in iD (Sat)= Kn/2(VGS-VTN)2 This expression indicates that the saturation drain current has no dependence on VDS.

28. Process Tranconductance parameter • It is to be noted that in the above expressions the parameter nCox is a constant determined by the processing technology used to fabricate the MOS technology. It is known as the process transconductance parameter, and is denoted by K'n= nCox • We can rewrite the conduction parameter in the form, Kn= K'nW/L Transistor design variable.

29. Current Determinates • For a fixed VDS and VGS (> VT), IDS is a function of • the distance between the source and drain – L • the channel width – W • the threshold voltage – VT • the thickness of the SiO2 – tox • the dielectric of the gate insulator (SiO2) – ox • the carrier mobility • for n: n = 500 cm2/ V-sec • for p: p = 180 cm2/ V-sec iD= Kn[(VGS-VTN)VDS-VDS2/2]

30. Short-channel effects • Short-channel device: channel length is comparable to depth of drain and source junctions and depletion width • In general, visible when L ~ 1m and below • Short-channeleffects: • Carrier velocity saturation • Mobility degradation • Threshold voltage variation

31. Carrier velocity saturation Vgs 0 Vds • Electric field Ey exists along channel • As channel length is reduced, electric field increases (if voltage is constant) • Electron drift velocity vd is proportional to electric field • only for small field values • for large electric field, velocity saturates N+ N+ source drain L P

32. Effects of High fields • Vertical field The vertical field occurs in the y-direction from the gate to the channel (EY=VDD/tox 1980 1995 2001 EY=5V/1000Ao =50 x 104V/cm EY=3.3.V/75Ao=4.4 x 106V/cm Ey=1.2V/22AO=5.5 x 106 V/cm • Horizontal field The horizontal field occurs in the x-direction from the drain to the source (EY=VDS/L 1980 1995 2001 Ex=5V/5mm =104V/cm Ex=3.3.V/0.35mm=9.4 x 104V/cm Ex=1.2V/0.1mm=1.2 x 105 V/cm

33. Carrier velocity saturation • Effect of velocity saturation: • Current saturates before “saturation region” • VDSAT = voltage at which saturation occurs • Drain current is reduced: (no longer quadratic function of VGS) • Saturation region is extended: VDSAT < VGS-VT

34. VGS = VDD Velocity Saturation Effects For short channel devices and large enough VGS – VT Long channel devices • VDSAT < VGS – VT so the device enters saturation before VDS reaches VGS – VT and operates more often in saturation Short channel devices VDSAT VGS-VT • IDSAT has a linear dependence wrt VGS so a reduced amount of current is delivered for a given control voltage

35. MOS ID-VGS Characteristics • Linear (short-channel) versus quadratic (long-channel) dependence of ID on VGS in saturation • Velocity-saturation causes the short-channel device to saturate at substantially smaller values of VDS resulting in a substantial drop in current drive X 10-4 long-channel quadratic ID (A) short-channel linear VGS (V) (for VDS = 2.5V, W/L = 1.5)

36. Short-channel and long channel comparison Long-channel Short-channel • Both devices have same effective W/L ratio I/V curves should be similar • Short-channel device has ~ 40% less current at high VDS • Note linear dependence on VGS in short-channel device

37. Threshold voltage variation • Until now, threshold voltage assumed constant • VT changed only by substrate bias VSB • In threshold voltage equations, channel depletion region assumed to be created by gate voltage only • Depletion regions around source and drain neglected: valid if channel length is much larger than depletion region depths • In short-channel devices, depletion regions from drain and source extend into channel

38. Threshold voltage variation Short-channel effects cause threshold voltage variation: • VT roll off • As channel length L decreases, threshold voltage decreases • Drain-induced barrier lowering • As drain voltage VDS increases, threshold voltage decreases • Hot-carrier effect • Threshold voltages drift over time

39. Threshold voltage variation • Even with VGS=0, part of channel is already depleted • Bulk depletion charge is smaller in short-channel device → VT is smaller N+ source N+ drain Drain depletion region Source depletion region Gate-induced depletion region

40. Threshold voltage variation • Change in VT0: • xdS, xdD: depth of depletion regions at S, D • xj: junction depth • VT0 is proportional to (xj/L) • For short channel lengths, VT0 is large • For large channel lengths, term approaches 0

41. Threshold voltage variations Graphically: VT0 versus channel length L Threshold as a function of As a function of length (for low VDS) Drain-induced barrier lowering (for low L) VT Roll-off:VT decreases rapidly with channel length

42. Threshold voltage variation • Hot-carrier effect • increased electric fields causes increased electron velocity • high-energy electrons can tunnel into gate oxide • This changes the threshold voltage (increases VT for NMOS) • Can lead to long-term reliability problems

43. Threshold voltage variation • Hot electrons • High-velocity electrons can also impact the drain, dislodging holes • Holes are swept towards negatively-charged substrate → cause substrate current- • Called impact ionization • This is another factor which limits the process scaling → voltage must scale down as length scales

44. CG4 M2 M4 CDB2 Vout Vout2 Vin CGD12 CDB1 M3 M1 CG3 Sources of Capacitance Vout Vin Vout2 CL Cw intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance

45. MOS Intrinsic Capacitances • Structure capacitances (oxide capacitance) • Channel capacitances • Depletion regions of the reverse-biased pn-junctions of the drain and source

46. n+ MOS Structure Capacitances (oxide) • Overlap capacitances • gate electrode overlaps source and drain regions • XD is overlap length on each side of channel • Leff = Ldrawn – 2LD • Total overlap capacitance: lateral diffusion Poly Gate Source n+ Drain n+ Top view Ld Ld W Ldrawn tox n+ Leff

47. MOS Channel Capacitances • Channel capacitances • Gate-to-source: Ggs • Gate-to-drain: Ggd • Gate-to-bulk: Ggb • Cutoff: • No channel connecting source and drain • Cgs = Cgd = 0 • Cgb = CoxWLeff • Total channel capacitance CC = CoxWLeff Cgs Cgd drain source Cgb

48. Gate capaciatnce- an example CC = CoxWLeff=WCg • Cg=CoxLeff Cg=Eox/tox(L)=(4)(8.85 x 10-14)/(1100Ao)(5mm)=1.6fF/mm) Cg=Eox/tox(L)=(4)(8.85 x 10-14)/(75Ao)(0.35mm)=1.6fF/mm) Cg=Eox/tox(L)=(4)(8.85 x 10-14)/(22Ao)(0.1mm)=1.6fF/mm) • This factor has reminded constant for over 25 years!

49. MOS Channel Capacitances • Linear mode • Channel spans from source to drain • Capacitance split equally between S and D The body electrode is shielded from the gate by the channel • Total channel capacitance CC = CoxWLeff

50. MOS Channel Capacitances • Saturation mode • Channel is pinched off: • Total channel capacitance CC = 2/3 CoxWLeff