Incremental Placement and Routing Algorithms for FPGA and VLSI Circuits

1. Incremental Placement and Routing Algorithms for FPGA and VLSI Circuits ShantanuDutt, ECE Primary Grant Support: National Science Foundation Partitioning Floorplanning Placement Routing Simul- ation • Current and future very deep submicron chips are so complex and minute that they need “corrections” or re-optimizations in small parts after initial design & simul. • Need to keep the correct parts of the chip as intact as possible – good resource usage, time-to-market req. • Need incremental CAD algorithms that re-do the “incorrect” parts fast and w/o significant effect on the correct parts • This project focuses on such incremental algorithms at the physical CAD or layout level of chip design – placement & routing Incr. Place VLSI CAD Flow: e.g., for timing closure • Use of a constraint-satisfying depth-first search (DFS) process that explores the design space for the incremental changes to: • Optimize them (e.g., power, critical path, signal integrity) • Subject to not deteriorating metrics of the larger unchanged chip beyond pre-set bounds (e.g., <= 10% increase in wire-length) • Use of a new network-flow based methodology to explore the design space in a more continuous manner (as opposed to discrete in DFS) for faster solutions: • Some approximations involved for discrete -> continuous optimization mapping • Incremental routing for FPGAs: • optimal DFS algorithmwrt # of tracks– if a solution exists will find it; 13 times faster than competitor VPR • Incremental routing for VLSI ASICs: • 98% success rate in completing routes – up to 9-12 times fewer failures than Std and R&R routers • Timing-driven incremental routing for VLSI ASICs: • 94% succ rate; 5 times fewer timing violations • Incremental placement for VLSI ASICs: • Prel results: applied to timing closure – 10% improv • Future Work: (1) Apply to timing, power closure via logic & circuit re-synthesis at the physical level + re-placement & re-routing; (2) Integration of incremental routing & placement