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FPGA Implementation of Denoising in OFDM Systems using DSP Design Module

FPGA Implementation of Denoising in OFDM Systems using DSP Design Module. Prof. Brian L. Evans PhD Students Jing Lin, Yousof Mortazavi , Marcel Nassar & Karl Nieman Wireless Networking and Communications Group Department of Electrical and Computer Engineering

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FPGA Implementation of Denoising in OFDM Systems using DSP Design Module

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  1. FPGA Implementation of Denoising in OFDM Systems using DSP Design Module Prof. Brian L. Evans PhD Students Jing Lin, YousofMortazavi, Marcel Nassar & Karl Nieman Wireless Networking and Communications Group Department of Electrical and Computer Engineering Cockrell School of Engineering The University of Texas at Austin May 10, 2012

  2. Outline | Background | System Design and Implementation | Conclusions Outline Part I • Algorithm Description • Project Goals • System Design and Implementation Part II • Demonstration Part III • Conclusions and Discussion

  3. Outline| Background | System Design and Implementation | Conclusions Impulsive Noise in Communication Systems • Antennas • Non-Communication • Sources • Electromagnetic radiation • Wireless Communication • Sources • Uncoordinated transmission • Baseband Processor • Noise Measurement • Computational Platform • Clocks, buses and processors • Other embedded transmitters • Background • Noise

  4. Outline| Background | System Design and Implementation | Conclusions Impulsive Noise in OFDM Systems • FFT spreads received impulsive noise across all FFT bins • SNR of each FFT bin is decreased • Receiver communication performance degrades Receiver y Equalizer and detector x IFFT Filter FFT + Vectorof symbolamplitudes(complex) Gaussian (g) + ImpulsiveNoise (e) Channel

  5. Impulsive Noise Mitigation (Denoising) • N FFT bins (tones) • Transmitter null tones have zero power • Received null tones contain noise • Impulsive noise estimation • Exploit sparse structure of null tones • FJis over complete dictionary • e is sparse vector • g is complex Gaussian (g = F w) Receiver y Equalizer and detector x + IFFT Filter FFT + + - Vectorof symbolamplitudes(complex) Impulsive noise estimation Gaussian (w) + ImpulsiveNoise (e) Channel |J| x N J is set of null tones (i.e. xj= 0)F is N x N FFT matrix

  6. Outline| Background | System Design and Implementation | Conclusions Sparse Bayesian Learning (SBL) Step 1: Maximum likelihood estimate of hyper-parameters Step 2: Estimate e from posterior mean: Matrix Inverse Matrix Multiply ~10dB ~6dB Norm

  7. Outline| Background | System Design and Implementation | Conclusions Project Goals From theory to implementation: • understand computational requirements • determine real-time constraints in target application • find feasible solution Steps involved: • develop floating-point model and simulator • fixed-point transformation • hardware/software partitioning • implementation

  8. Outline| Background | System Design and Implementation | Conclusions System Design and Implementation Using NI Products RT Host (software) NI LabVIEW RT Simulator SBL Software NI Embedded Controller (NI PXIe-8133) SBL Hardware Chassis NI LabVIEWFPGA DSP Design Module FPGA (hardware) NI Flex RIO (NI PXIe-7965R) NI PXIe Chassis (NI PXIe-1082)

  9. Outline| Background | System Design and Implementation | Conclusions Current Hardware/Software Partitioning SBL Software N = 128 M = 32 (diagonal) scalar SBL Software SBL Hardware SBL Hardware

  10. Outline| Background | System Design and Implementation | Conclusions Computational Requirements for Powerline Communications Major operations • N-point fast Fourier transform (N=128) • vector dot product (length 32, 128) • matrix-vector multiplication (32x128) x (128x1) • matrix-matrix multiplication (128x32) x (32x128) • matrix inversion (32x32) • multiple iterations per symbol (30 or more) Real-time requirement processing time < OFDM symbol duration (231.7- 2240 µs)

  11. Outline| Background | System Design and Implementation | Conclusions FPGA hardware design using NI DSP Design Module DSP Diagram implements • FFT (N=128) • accumulators, adders, subtracters, multipliers • vector scaling (element-by-element) • 2-norm calculation (squaring + accumulating)

  12. Outline| Background | System Design and Implementation | Conclusions Fixed Point Transformation

  13. Outline| Background | System Design and Implementation | Conclusions Fixed Point Model of Computations in FPGA

  14. Designing Wordlengths • MATLAB • Displays statistics • Allows analysis of bit allocation • Graphical control • Automatic Settings • LabVIEW • Used max/min (absolute value) to understand range at each node • Saturation indicators • Tedious manual process • Better to iterate in LabVIEW RT than on FPGA

  15. Outline| Background | System Design and Implementation | Conclusions Compile Results FPGA hardware implementation can exploit parallelism by using more adders and multipliers! Parallelism and pipelining can increase the maximum frequency.

  16. Outline| Background | System Design and Implementation | Conclusions Advantages of NI DSP Design Module FPGA implementation is greatly simplified! Good level of abstraction to focus on algorithm development and increase productivity, rather than worry about: • clock domains • FIFOs and sizing • handshaking (e.g. data valid, ready for input, output ready, etc.) • DMA transfers between FPGA and host • etc. Can do a lot with very little/no LabVIEW FPGA coding Automatic test bench generation also very useful!

  17. Outline| Background | System Design and Implementation | Conclusions More advanced use of NI DSP Design Module Matrix operations are not currently supported May create custom “DSP Blocks” to load in DSP Diagram Custom (high performance) blocks are coded in LabVIEW FPGA at a lower abstraction (requires more experience) Implemented a 32x32 matrix-matrix complex multiply using 128 (out of 640) hardware multipliers on Virtex-5 SX95T FPGA

  18. Outline| Background | System Design and Implementation | Conclusions Example 32 Element Vector Dot Product Can make high performance blocks, with a little wiring!

  19. Outline| Background | System Design and Implementation | Conclusions Example 32x32 Matrix Matrix Multiply

  20. Outline| Background | System Design and Implementation | Conclusions LabVIEW FPGA IP Builder • Fortunately, a new NI product called IP Builder can simplify custom hardware design using more “software-like” structures

  21. Outline| Background | System Design and Implementation | Conclusions DEMO

  22. Outline| Background | System Design and Implementation | Conclusions Future Work at UT Implement more blocks in hardware • Use IP Builder for matrix operations • QR decomposition in FPGA • Inversion with QR Develop sequential version of algorithm with hardware implementation in mind Use ADC/DAC and physical channel instead of simulator

  23. Thank you for your attention!

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