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Low-Density-Parity-Check Decoder. Yu- Hsin Chen Yi- Ju Chen Genius Prof. Andy Wu 2008/07/03. Group Mentor Adviser Date. Project FINAL presentation. OUTLINE. C++ Floating Point Simulation C++ Fixed Point Simulation Wordlength Decision Methods CNU Unit Survey Conclusions
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Low-Density-Parity-Check Decoder Yu-Hsin Chen Yi-Ju Chen Genius Prof. Andy Wu 2008/07/03 Group Mentor Adviser Date Project FINAL presentation
OUTLINE • C++ Floating Point Simulation • C++ Fixed Point Simulation • Wordlength Decision Methods • CNU Unit Survey • Conclusions • Future Work • References
C++ Floating Point Platform Data Generation Analysis Decoding Decoding Signal Transmission Decoder Decoder Decoder MSA Decoder MSA Decoder MSA Decoder SPA Decoder MSA Decoder LDPC Matrix LDPC Matrix LDPC Matrix LDPC Matrix LDPC Matrix AWGN AWGN AWGN AWGN AWGN MSA Check Node Update MSA Check Node Update MSA Check Node Update SPA Check Node Update MSA Check Node Update SPA Check Node Update Bit Node Update Bit Node Update Bit Node Update Bit Node Update Bit Node Update Initialization Initialization Initialization Initialization Initialization LDPC Codeword LDPC Codeword LDPC Codeword LDPC Codeword LDPC Codeword BPSK BPSK BPSK BPSK BPSK Decision Decision Decision Decision Decision BER PER BER PER BER PER BER PER BER PER Compare Compare Compare Compare Compare
802.16e Parity Check Matrix Ip*p Cyclically Shifted by x X p = 24, 28, …, 96 (19 Modes) p 12*24 Base Parity Check Matrix
Floating Point Simulation SNR-BER for MSA SNR-BER for SPA Both Perform Better Using Larger Extension
C++ Fixed Point Platform Fixed Wordlength MSA Decoder LDPC Matrix AWGN MSA Check Node Update Bit Node Update Initialization LDPC Codeword BPSK Decision BER PER Compare
Fixed Point Simulation (1/2) MSA p = 96 SNR-BER Fixed Integer Part = 3 Fixed Integer Part = 4 Fixed Integer Part = 2 Integer Part = 4 Line Very Close to Integer Part = 5 Line Integer Part = 3 Performs Similar to Integer Part = 4 BER Decrease Rate↓ As Fractional Part ↑
Fixed Point Simulation (2/2) MSA p = 96 SNR-BER Fixed Fractional Part = 3 Fixed Fractional Part = 4 Fixed Fractional Part = 2 BER Decrease Rate↓ As Fractional Part ↑ Fractional Part = 3 Performs Similar to Fractional Part = 4 Integer Part = 4 Line Very Close to Integer Part = 5 Line
Wordlength Decision Fixed Fractional Part = 4 Bits Fixed Integer Part = 4 Bits SNR Around 0.2 dB A Good Choice Found Integer Part = 4 bits Fractional Part = 4 bits BER Saturated With Fractional Part ≥ 4 Choose Fractional Part = 4 BER Saturated With Integer Part ≥ 4 Choose Integer Part = 4
Wordlength Decision – 3D View SNR = 0.4dB BER BER Fractional Part (Bits) Integer Part (Bits) Integer Part (Bits) Fractional Part (Bits)
Wordlength Search Method (1/2) • Several Wordlength Search Methods: [1] • Ex: Complete Search Test Each Combination Fractional Part (Bits) 6 5 4 3 2 1 Points Traversed = # of Points in the Bound Integer Part (Bits) 1 2 3 4 5 6
Wordlength Search Method (2/2) • Several Wordlength Search Methods: [1] • Or Exhaustive Search Test By Wordlength Fractional Part (Bits) 6 5 4 3 2 1 Points Traversed = 1+2+…+(n-1) = n*(n-1)/2 Optimum Point Integer Part (Bits) 1 2 3 4 5 6
Our Method: Binary Search (1/2) • Binary Search: • Search by Same Wordlength • Test Only 2 Points at a time 3, 1 4, 1 1, 4 [ Integer, Fractional ] Wordlength 2 1, 1 Test Path of Exhaustive Search Test Path of Binary Search 3 2, 1 1, 2 4 2, 2 1, 3 3, 1 5 3, 2 2, 3 4, 1 1, 4
Our Method: Binary Search (2/2) • 1st Iteration Wordlength = 3 bits • 5th Iteration Wordlength = 7 bits • 4th Iteration Wordlength = 6 bits • 3rd Iteration Wordlength = 5 bits • 2nd Iteration Wordlength = 4 bits • Start With (Integer, Decimal) = (1, 1) BER = 2.2*10-6 < 3.0*10-6 Terminate ! Fractional Part (Bits) Termination Condition: BER < 3.0*10-6 6 5 4 3 2 1 3.3*10-6 2.2*10-6 Integer Part Fractional Part 1.4*10-5 5.0*10-6 1.0*10-4 2.0*10-5 0.0020 0.0003 Smaller Smaller Smaller 0.012 Smaller Smaller 0.008 Integer Part (Bits) 1 2 3 4 5 6 BER
BER Decrease Rate BER (2, 2) (2, 3) (2, 3) Differentiation(Slope) With Bit Bit Efficiency (3, 2) (3, 2) Integer Part (Bits) Fractional Part (Bits)
Decoder Hardware Overview LDPC Decoder MSACheck Node Update MSACheck Node Update Bit Node Update Bit Node Update Initialization Decision Storage element MemoryKey: Usage Efficiency 2. MSA CNU Unit Find Min. 3. BNU Unit Addition • Y = sign(X1)sign(X2)…sign(Xn).min(|X1|, |X2|, …, |Xn|)
CNU Unit Implementation • Find Minimum Among N Data • Compare 2 Numbers at a time • Ex: N=7 • Find Minimum Among N Data • Compare 3 Numbers at a time [2] Trade Area for Speed • Ex: N=7 Data3 Data4 Data5 Data6 Data1 Data2 Min Min Min A = MSB[ Data1 – Data2 ] B = MSB[ Data3 – Data2 ] C = MSB[ Data1 – Data3 ] Min Data4 Data5 Data6 Data1 Data2 Data3 Min3 Min3 A Min Minimum 1 0 Data1 Min 1 0 Data7 Min3 Minimum Data2 Minimum MSB[ Data1 – Data2 ] 0 1 Data1 Data2 3 Stages !! Min Minimum 2 Stages !! C Data1 1 0 MUX Data3 Data7 log2N Stages For N Data ! Minimum log3N Stages For N Data ! Min3 B Data2
CNU Unit Improvement • Min3 Unit with Subtractor Subtractor Our Modified Comparator Min3 Unit with Comparator D1[n] D2[n] D1[n] D2[n] D1[2] D2[2] D1[2] D2[2] D1[1] D2[1] D1[1] D2[1] D1[0] D2[0] D1[0] D2[0] Bit Compare Unit Bit Compare Unit Bit Compare Unit Bit Compare Unit FA FA FA FA … … MSB MSB[ Data1 – Data2 ] Compare [Data1, Data2] 1 0 1 0 Data1 Data1 = MSB of Subtractor 1 0 1 0 Minimum Minimum Data2 Data2 0 1 0 1 Compare [Data1, Data3] MSB[ Data1 – Data3 ] 17.9% Smaller ! Data3 Data3 Simplified Computation Slightly Faster ! Compare [Data3, Data2] MSB[ Data3 – Data2 ]
CONCLUSIONS • This semester, we learned: • How LDPC Works • SPA MSA • Floating/Fixed Point Simulation • Wordlength Decision Binary Search • BER Decrease Rate Bit Efficiency • CNU Unit • Reduction of Computational Stages • Subtractor Our Modified Comparator
FUTURE WORK • Algorithm Improvement: • Hardware Implementation: BER • Normalized-MSA • Offset-MSA • Our Proposed Method … SNR(dB) • CNU Unit Improvement • Memory Usage Efficiency • Units Connection Memory CNU BNU
REFERENCES [1] Kyungtae Han, Brian L. Evans, ”Optimum wordlength search using sensitivity information,” EURASIP Journal on Applied Signal Processing, Volume 2006, Issue 1, pp. 76 – 76, 2006. [2] Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu Wu, “An 8.29mm2 52mW Multi-mode LDPC Decoder Design for Mobile WiMAX System in 0.13um CMOS Process ,” IEEE Jour. Solid-State Circuits, vol. 43, no. 3, pp. 672-683, Mar. 2008. [3] X. Y. Hu, E. Eleftheriou, D. Arnold, and A. Dholakia,“Efficient Implementations of the Sum-Product Algorithm for Decoding LDPC Codes, " IEEE Global Telecommun. Conf., vol. 2, pp. 1036-1036E, Nov. 2001. [4] R. G. Gallager, “Low-density parity-check code, ” IEEE Trans. Inform. Theory, vol. IT-8, pp. 21-28, Jan. 1962. Thank You!! Q&A