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Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs

Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs. Gengxin Hua, Hongjin Liu, Bo Liu Beijing Institute of Control Engineering. Keheng Huang, Yu Hu, Xiaowei Li Institute of Computing Technology Chinese Academy of Sciences. 2011-11-23. Purpose.

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Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs

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  1. Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs Gengxin Hua, Hongjin Liu, Bo Liu Beijing Institute of Control Engineering Keheng Huang, Yu Hu, Xiaowei Li Institute of Computing Technology Chinese Academy of Sciences 2011-11-23

  2. Purpose • Soft error mitigation scheme . • SRAM-based FPGAs • Utilize logic masking effect • During logic synthesis • Without additional area overhead

  3. Outline • Background . • Motivation • FEC-based soft error mitigation scheme • Experimental results • Conclusions

  4. Outline • Background . • Motivation • FEC-based soft error mitigation scheme • Experimental results • Conclusions

  5. Background • Architecture of SRAM-based FPGAs .

  6. Background • Architecture of SRAM-based FPGAs .

  7. Background • Architecture of SRAM-based FPGAs .

  8. Background • Architecture of SRAM-based FPGAs . 97% 3% SRAM bits

  9. Background • Architecture of SRAM-based FPGAs . 97% 3% SRAM bits 70% The reliability of routing resources is of great importance, and needs to be seriously considered

  10. Background • FPGA EDA flow . Design specification Synthesis and mapping Gate-level netlist Placement and routing Bit Stream

  11. Background • FPGA EDA flow . • ROSE[Hu, ICCAD’08], IPR[Feng,ICCAD’09], R2[Jose, DAC’10] • Boolean matching • High computational complexity • Dual-output resynthesis[Lee, ASP-DAC’10] • LUT Dual-output encoding • Relies on dual-output feature of FPGAs Design specification Synthesis and mapping Gate-level netlist Placement and routing Bit Stream

  12. Outline • Background . • Motivation • FEC-based soft error mitigation scheme • Experimental results • Conclusions

  13. Motivation • There are a lot of free LUT entries (all 6 LUT inputs are used%=43.71%), which can be used to mitigate soft errors

  14. Outline • Background . • Motivation • FEC-based soft error mitigation scheme • Experimental results • Conclusions

  15. FEC-based soft error mitigation • Logic masking effect .

  16. FEC-based soft error mitigation • Address Hamming Distance . • The Hamming Distance between the addresses of two LUT entries • If (H[addr(entry0, entry2)]=H[00,10]=1) && the configuration bits are the same Then, the fault at corresponding inputs will be logic masked

  17. FEC-based soft error mitigation • Flowchart of the design .

  18. FEC-based soft error mitigation • Establishing FEC models .

  19. FEC-based soft error mitigation • Establishing FEC models .

  20. FEC-based soft error mitigation • Cube-based reliability analysis . • Evaluate the reliability of each LUT input • FEC replacement with most reliability improvement • One free LUT input • FEC 1.x: • Two free LUT inputs • FEC 2: • More than two LUT inputs • Combination of FEC 1.x and FEC 2 Keheng Huang, Yu Hu, Xiaowei Li, “Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation,” in Proc. of DATE, 2011. pp.58-63

  21. Outline • Background . • Motivation • FEC-based soft error mitigation scheme • Experimental results • Conclusions

  22. Experimental results • Hardware: • Xeon 6GB Workstation • Software: • Java MCNC benchmark set • Synthesis and • mapping：Berkeley ABC mapper • Architecture of FPGA: • 4 6-input LUTs/CLB • Virtex like routing Gate-level netlist • Placement and • Routing：VPR toolset SRAM bits

  23. Experimental results • Area . • # of LUTs • Soft Error Rate (SER) • Cube-based reliability analysis • Critical-path delay • Reported by VPR • Computational complexity • Runtime

  24. Experimental results • Area . • # of LUTs • No area overhead

  25. Experimental results resynthesis: • SER : reduced by 21.72% . • ROSE:25% • IPR:49% • Dual-output 27%

  26. Experimental results • Critical-path delay . • Reported by VPR • Increased by 4.25%

  27. Experimental results resynthesis: • Computational complexity . • Runtime : 28.83ms • ROSE:184.2s • IPR:5.58s • Dual output 6s

  28. Outline • Background . • Motivation • FEC-based soft error mitigation scheme • Experimental results • Conclusions

  29. Conclusions • FEC-based soft error mitigation . • Mitigate Soft Errors in FPGA • Reduce SER by 21% • Small performance overhead • Critical-path delay increase: 4.25% • No area overhead (exploiting free LUT entries) • Does not rely on specific FPGA devices • Suitable for all LUT based FPGAs

  30. Q & A

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