Pipelining and Retiming

1. Pipelining and Retiming Prepared by Mark Jarvin

2. Agenda • Synchronous circuit retiming • Pipelining • Software pipelining

3. The Retiming Problem: Example • D = 4 • T = 4 • Latency = 4 • Throughput = 4 • How can this be improved? • Pipelining?

4. The Retiming Problem: Example • Latency = 6 • Throughput = 3 • Delay is not balanced • This can still be improved

5. The Retiming Problem: Example • Latency = 4 • Throughput = 2 • Now, delay is balanced

6. Observations • Some basic transformations can be used for cycle time reduction • The retiming transformation moves registers across gates

7. Observations • Levelization doesn’t help • Only useful for acyclic circuits

8. Naïve Algorithm while ( not timed ) { pick a candidate gate; apply retiming transformation; do timing analysis; }

9. Questions • Can we apply retiming in batch mode? • i.e., simultaneously on all gates • Can we make sure the retimed circuit is optimal? • Can we achieve this in polynomial time?

10. Retiming Circuit Model

11. Retiming Circuit Model: Example 1

12. Retiming Circuit Model: Example 1

13. Retiming Circuit Model: Example 2

14. Metrics • Path delay: • Path weight:

15. Metrics • Define weight and delay metrics for any given vertex pair: • Both quantities are undefined if there is no path p from u to v

16. W (D) Matrix for Example 2

17. The Retiming Transformation • How do we represent retiming? • How does it affect G? • Informally: • The transformation is fundamentally moving registers across gates • Represent it as the number of registers to push from a gate’s outputs to its inputs • Define this number for all gates

18. The Retiming Transformation • Definition: a retiming of a network is an integer-valued vertex labelling that transforms into where for each edge :

19. The Retiming Transformation • Initially: • Apply retiming: • Finally: • Note: retiming will change the number of registers in general, but not the number of registers in a given cycle

20. Legal and Feasible Retiming • A retiming is legal if the retimed network doesn’t contain negative weights: • For a given cycle time , the network is timing feasible if it can correctly operate under • This holds if for all

21. Feasible Retiming • Furthermore: • Finally:

22. Feasible Test Algorithm • Any retiming must satisfy the system of difference constraints: • General approach: integer linear programming • Special form: single-source longest path problem • Note: we can skip the second inequality wherever or

23. Feasible Test Algorithm • Longest path problem can be solved with Bellman-Ford • Build a constraint graph with an edge from i to j if we have a constraint of the form

24. Feasible Test Algorithm • The solution is feasible if there are no positive cycles • If feasible, the longest distance of each vertex provides the retiming function • For the previous example, with reference node vh: • There are no positive cycles; hence, is a feasible clock period

25. Feasible Test Algorithm • Here, there is a positive cycle: • Hence, a clock period of 12 is not feasible

26. Optimally Retimed Example Circuit

27. Optimal Retiming • Binary search of minimum cycle time optimalRetiming ( G ) { min = 0; max = MAX; while ( min ≠ max ) { mid = ( max – min ) / 2; if ( feasibleTest ( G, mid ) ) max = mid; else min = mid; } return min; }

28. Optimal Retiming • Do we really need to search all clock periods? No… • Optimal cycle time must be one of D(i,j) • So, sort and search O(V2) clock periods • Computing each D(i,j) requires O(VE+V2 lgV) time • Overall, the complexity is O(VE lgV)

29. Optimal Retiming • Can we do better? Yes… • Look at the delay-to-register ratios and maximum node delay of the cycles in the circuit, where delay-to-register ratio and maximum node delay are defined as: • Then, the minimum feasible clock period lies in the range: • This improves the overall running time to O(VE lgD)

30. Pipelining • Can be thought of as a special case of retiming

31. Software Pipelining • This can also be thought of in terms of retiming