Pipelining and Hazards

1. Pipelining and Hazards • Hazards occur because • Don’t have enough resources (ALU’s, memory,…)Structural Hazard • Need a value that is not yet thereData Hazard Why would this happen? - Program specifies instructions in the correct order - We compute things in the correct order - But we write to memory/registers in a later cycle than when values are read for computation • Can’t compute address of the next instruction correctlyControl Hazard • In essence, all three problems arise because of the way our pipeline is designed and the order in which instructions are presented. • Can therefore get rid of (or reduce the penalty of) some of the hazards by • restructuring our pipelineHardware solutions • presenting instructions to the hardware in a better mannerCompiler Solutions Ashish Sabharwal

2. Hazards vs. dependencies • Dependencies are a property of the code • Instructions do need to use values computed by previous instructions! • Compiler can sometimes help give us a better code, but we may still have dependencies • Hazards are a property of code + implementation • No hazards on single cycle / multi cycle implementations • Three kinds of dependencies • Read after write (RAW) - don’t want to read a value that has not been written yet - the one we have been looking at - the most natural dependency • Write after read (WAR) - don’t want to overwrite a value that had to be read by some intermediate instruction - required for correctness - Why doesn’t this cause trouble in our pipeline ? • Write after write (WAW) - if a register/memory location is being written twice, I want to preserve the order in which they are written - required for correctness - why doesn’t this cause trouble in our pipeline ? • What about Read after Read ? Ashish Sabharwal

3. The assignment - 1 • 6.9. “… determine as much as you can about the five instructions in the five pipelining stages”, given values of control signals and some of the instruction fields. • Easy • Just look carefully at each field/control value • Difficult part: Need to determine something about all 5 instructions given a snapshot at some cycle. • 6.12. Given a piece of assembly code, “explain what the forwarding unit is doing during the fifth cycle of execution.” Mention any comparisons that are being made. • Fill the pipeline with 5 instructions • You know all register specifiers at this stage and also know what registers need to be compared • 6.14. Given a sequence of 100 lw instructions, each dependent on the previous, how long will it take to execute them? • Every instruction is dependent on the previous one • Compute the number of cycles you need to stall between every two instructions • Remember the time needed to fill the pipeline Ashish Sabharwal

4. The assignment (2) • 6.19. Situation 1:add $2, _, _ add _, $2, _Situation 2: sw _, _($2) lw _, _($2)How do these situations differ in terms of hazards on our pipeline? • (We already talked about hazards given dependencies) • 6.20. Memory to memory copy:lw $2, 100($5) sw $2, 200($6)What additional forwarding hardware can be used to improve performance for such a sequence? • We already have a mechanism for better performance for load followed by its use in an ALU op • Do something similar for load followed by store. • Easy! Ashish Sabharwal

5. The assignment (3) • 6.26. Is there a code sequence for which, at some cycle, we generate signals to flush a pipeline as well as to stall?beq $1, $2, TARGET # assume “taken” lw $3, 40($4) add $3, $3, $3 sw $3, 40($4)TARGET: or $10, $11, $12Do some of the resulting actions cooperate? Do some of the resulting actions conflict? If yes, how can you modify the pipeline to take care of this? • 6.31. Loop unrollingGiven a loop, unroll it to make 3 copies for each iteration. (Note: number of iterations may not be a multiple of 3 !) Now reschedule the code to avoid hazards as far as possible.How much faster is the new code (include stalls)? Ashish Sabharwal

6. The assignment (4) • Loop unrolling: Original -Loop: lw $t0, 0($s1) addu $t0, $t0, $s2 sw $t0, 0($s1) addi $s1, $s1, -4 bne $s1, $zero, LoopUnrolled once to make 2 copies -Loop: lw $t0, 0($s1) addu $t0, $t0, $s2 sw $t0, 0($s1) lw $t0, -4($s1) addu $t0, $t0, $s2 sw $t0, -4($s1) addi $s1, $s1, -8 bgt $s1, 4, Loop beq $s1, $zero, Done< do something here ! >Done: • Code scheduling:Try to “space-out” producer and consumer by adding independent instructions in-between. Ashish Sabharwal

7. The assignment (5) • What happens if we change the pipeline to have the following stages ? IF1 IF2 ID EX MEM1 MEM2 WBWhat hazards are possible?What needs to be forwarded to which stage to avoid these hazards? • Instruction fetch takes 2 cycles instead of 1 • Memory access takes 2 cycles instead of 1 Ashish Sabharwal