Techniques for Test Power Reduction in Leading Edge IP Using Cadence Encounter Test - ATPG

1. Techniques for Test Power Reduction in Leading Edge IP Using Cadence Encounter Test -ATPG: By Praveen Venkataramani

2. Objective • To reduce dynamic power during test in scan based designs • To obtain test vector sequences with minimum switching and pattern count without any loss in test coverage

3. Overview[1] • Test power consumption is 3x – 5x the functional power • Can cause false failures due to IR drop as a result of high switching in scan test • Shift Power • Cause • High toggle during shift • Fix • Reduction in overall toggle activity- Use fill techniques • Capture Power • Cause • Toggle Activity due to circuit response • Fix • Using clock gating technique – Functional clock is gated from areas that are not required for functional operation at that time 3

4. Experimental Setup • 45nm Cortex A8 ARM IP • Functional clock - 600 MHz • Flop Count – 130,000 • Clock Domains – 5 (only 1 Domain with 97%of flops is used for the experiments) • Launch on Capture • Length of Scan chains • FULSCAN – 8 chains • Average chain length : 17281 flip flops • Longest chain length : 17344 flip flops • Compression- 904 chains • Average chain length: 152 flip flops • Longest chain length: 155 flip flops • Tool Used – Cadence Encounter Test (Cadence ET) • Default setting • Compaction Effort – Ultimate • Fill – Random fill • All Flops switch at capture

5. Vector Compression

6. Vector Compression • Multiple chips are tested on an automated test equipment (ATE). • Number of available scan channels(ports) from ATE is small compared to the ports in the CUT • Available storage in ATE for test vectors • Need for decompress and compress the test vectors used for test

7. Compression Structure[2]

8. Compression Modes • Broadcast • One channel from the ATE fanouts (“broadcasts”)to multiple scan chains • Using XOR gates • The vector on the scan chain is a function of the input and the XOR gates

9. Broadcast Decompression/Spreader Broadcast spreader XOR Compression Masking logic ATE Scan Chain 1 ATE Scan Chan 2 Scan Chain 3 Scan channels Scan Chain n-2 Compressed Output Scan Chain n-1 Scan Chain n Mask Enable pins Scan Enable Pin Internal Clock generator Tester clock pin

10. XOR Spreader and Decompressor XOR spreader XOR Compression Masking logic ATE ATE Scan Chain 1 Scan Chan 2 Scan channels Scan Chain 3 Scan Chain n-2 Compressed Output Scan Chain n-1 Scan Chain n Mask Enable pins Scan Enable Pin Internal Clock generator Tester clock pin

11. Channel Masking

12. Channel Masking X X X X X X X X To ATE From the Scan chains X X

13. Channel Masking- Types [3] Types Wide 0, Wide1, Wide 2 CUT uses Wide2 Mask logic Contains 2 Mask registers R0 and R1 Mask register is pre-loaded before scan out. Sets the ‘X’ to value in the Mask bit Prevents output data from corruption Some good values could be masked

14. Scan Shift Toggle Reduction

15. Fill Techniques in Cadence ET[4] • Toggle activity during scan test is high • Reduce toggle activity using fill techniques • Random • Repeat • ‘0’ or ‘1’ • Method 1: explicitly specify the fill technique • Method 2: specify the allowed percentage toggle activity • Method 3: Dual fill, combination of repeat and random fill.

16. Filling of “Don’t-care” Bits- Fullscan Mode (Cadence ET®)

17. Filling of “Don’t-care” Bits- Fullscan Mode (Cadence ET®)

18. Average Toggle Activity during scan shift in Fullscan Mode

19. Fault Analysis-Fullscan Mode

20. Summary of Percentage Reduction in Peak Toggle Activity

21. Average Power Analysis using Synopsys PrimeTime-PX [5]- Fullscan mode

22. IR Drop Analysis

23. IR Drop • IR Drop occurs due to interconnect resistance between VDD to cell or macro • VDD domains vdd_mpu and vddlsw_mpu result in maximum IR drops • For proper operation of the circuit, the minimum allowable voltage must not be below15% of the reference VDD, in this case 1.08 V.

24. Max Dynamic IR Drop Gradient map-Random Fill vector

25. Max Dynamic IR Drop Gradient map- Repeat Fill Vector

26. Switching Histogram- Random Fill Vector

27. Switching Histogram- Repeat Fill Vector

28. Scan Capture Toggle Reduction Reason for toggle during scan capture What is clock gating? Results from Cadence ET

29. Capture Toggle • Capture toggle occurs due to the circuit response • Difficult to control through scan in vectors • Option- to mask the flip flops that don’t need to be toggled • Use clock gates available in the circuit

30. Clock gate Information of the CUT

31. Toggle Activity during Capture- Fullscan

32. Future work • Pattern Generation and analysis for reduction in toggle activity during scan capture. • Use the generated vector on ATE to test the CUT

33. References • Ravi, S. , "Power-aware test: Challenges and solutions," Test Conference, 2007. ITC 2007. IEEE International , vol., no., pp.1-10, 21-26 Oct. 2007 doi: 10.1109/TEST.2007.4437660 • http://www.cadence.com/rl/Resources/conference_papers/3.7Presentation.pdf • Vivek Chickermane, Brian Foutz, and Brion Keller. 2004. Channel Masking Synthesis for Efficient On-Chip Test Compression. In Proceedings of the International Test Conference on International Test Conference (ITC '04). IEEE Computer Society, Washington, DC, USA, 452-461. • Encounter Test Low Power user guide • Synopsys PrimeTime PX user guide • Apache Redhawk user guide • “The Power of RTL Clock-gating”, by Mitch Dale, http://chipdesignmag.com/display.php?articleId=915