1 / 39

Digital Testing: Fault Simulation

Digital Testing: Fault Simulation. Fault Simulation. Classical Fault Simulation Modern Fault Simulation for Combinational Circuits Modern Fault Simulation for Synchronous Sequential Circuits Parallel and Distributed Fault Simulation Fault Grading --- Approximate Fault Simulation

ethan-garner
Download Presentation

Digital Testing: Fault Simulation

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Digital Testing:Fault Simulation Based on text by S. Mourad "Priciples of Electronic Systems"

  2. Fault Simulation • Classical Fault Simulation • Modern Fault Simulation for Combinational Circuits • Modern Fault Simulation for Synchronous Sequential Circuits • Parallel and Distributed Fault Simulation • Fault Grading --- Approximate Fault Simulation • Hardware Approaches to Fault Simulation

  3. Why Fault Simulation? 1. To evaluate the quality of a test set -- usually in terms of fault coverage 2. To incorporate into ATPG for test generation -- due to its lower complexity 3. To construct fault dictionary -- for post-test diagnosis 4. To analyze the operation of a circuit in the presence of faults -- for reliability analysis

  4. Patterns (Sequences) (Vectors) Response Comparison Faulty Circuit #F (D/0) Faulty Circuit #2 (B/1) Detected? Faulty Circuit #1 (A/0) Fault-free Circuit Primary Inputs (PIs) A B D C Primary Outputs (POs) Conceptual Fault Simulation • Logic simulation on both good (fault-free) and faulty circuits

  5. Verification input stimuli Verified design netlist Fault simulator Test vectors Modeled fault list Test compactor Remove tested faults Delete vectors Fault coverage ? Low Test generator Add vectors Adequate Stop Fault Simulation

  6. Generate initial T No more faults Select target fault Evaluate T done Generate test for target Sufficient fault coverage? Y N Fault simulate done Modify T Discard detected faults Fault simulation To evaluate (grade) a test T use fault simulation Selection of target faults

  7. Classical Fault Simulation • Common Characteristics: • In general, no restriction on the circuit types. • Developed before VLSI era. • Serial Fault Simulation • trivial single-fault single-pattern • Parallel Fault Simulation • Deductive Fault Simulation • Concurrent Fault Simulation

  8. #Gate (G) #Fault (F) #Pattern (P) Complexity of Fault Simulation • Complexity = P * F *G~ O(G3) with single s-a faults • The complexity is higher than logic simulation, O(G2), • but is much lower than test pattern generation. • In reality, the complexity is much lower due to fault • colapsing and advanced techniques.

  9. Serial fault simulation • fault specification (includes fault collapsing) • fault insertion • fault effect generation & propagation • fault detection & discarding In parallel fault simulation, a number of faulty circuits are simulated and signal values are represented by vectors

  10. Classical Parallel Fault Simulation • Taking advantage of inherent parallel operation of computer words to simulate faulty circuits in parallel with fault-free circuit • the number of faults, that can be processed in parallel is limited by the word length. • Straightforward and memory efficient • Some weaknesses: • A value change, of a single fault or fault-free circuit leads to the computation of the entire word. • The fault-free logic simulation is repeated for the number of passes.

  11. Consider three faults: B/1, F/0, and J/0 • Bit-space: J/0 B/1 F/0 FF where FF = Fault-free 1 1 1 1 A 1 0 1 0 0 0 1 0 1 0 1 0 0 C G 0 x 1 1 0 1 1 x D E B 0 0 0 0 H J 1 1 0 1 x 1 1 0 0 1 F 1 1 1 1 1 1 0 1 Example of Parallel Fault Simulation

  12. Parallel Fault Simulation Applied test pattern: abcde=10010

  13. ff a /0 b /1 c /1 d /0 e /1 f /0 f /1 g /0 g /1 h /0 h /1 i /0 i /1 u/ 0 u /1 a =1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b =0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 c =0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 d = 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 f = ab 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 g =( f + c)’ 1 1 0 0 1 1 1 0 0 1 1 1 1 1 1 1 h = cd 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 e =0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 i = e + h 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 u = g + i 1 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 Parallel Fault Simulation

  14. 0 1 2 3 4 5 6 7 8 9 F 1 1 1 1 0 1 1 0 1 1 ... 1 Deductive fault simulation Instead of keeping all signal values for all faulty circuits in parallel as in parallel simulation, only a list of faults which causes different responses on a given line is kept faults signal line i parallel deductive Li = {4, 7}

  15. a = 1 f=0 G1 g=1 b=0 f=0 Lf =( - )È L L f/1 b a G2 - )È L =(L L (u/0) c=0 g=1 È È u g i L =L L g/0 g f c G5 u=1 i=0 c=0 h=0 h=0 i=0 G3 G4 d=1 È È i/1 L =L L i h e e=0 Lh = - )È (L L h/1 c d x=1 x=1 x=1 x=1 y=0 y=0 y=1 y=0 z=0 - - È È - L L L (L L ) L L L L x y x y z x y y x Deductive Fault Simulation (a) Gate rules (b)

  16. Æ È È Å If C = then L = { L } {Z sa(c i)} z j Î j I Ç È È Å else L = ({ L } - { L }) {Z sa( c i)} j j Î Î j C j I - C Rules for deductive simulation Therefore for AND,OR,NAND,NOR there is no 0,1,0 or 1 respectively on any input and append the output list list with Z/0, Z/1, Z/1, Z/0 respectively I - input c - controlling values i – inversion value and for the primary inputs set So for AND,OR,NAND,NOR when there is 0,1,0 or 1 on their inputs append output list with Z/1, Z/0, Z/0, Z/1 respectively

  17. c i |c| = 0 |c| > 0 fault fault equivalence dominance AND 0 0 Z0 Z1 I0  Z0 I1 < O1 OR 1 0 Z1 Z0 I1  Z1 I0 < O0 NAND 0 1 Z1 Z0 I0  Z1 I1 < O0 NOR 1 1 Z0 Z1 I1  Z0 I0 < O1 Deductive fault simulation Besides faults which can propagate through the gate, we add the following output faults

  18. Deductive fault simulation For two-input gates

  19. a = 1 f=0 G1 g=1 b=0 f=0 Lf =( - )È L L f/1 b a G2 - )È L =(L L (u/0) c=0 g=1 È È u i g L =L L g/0 LEVEL 0 LEVEL 1 LEVEL 2 LEVEL3 LEVEL4 Node FF PRIMARY INPUTS PRIMARY OUT a 1 a/0 b 0 b/1 c 0 c/1 d 1 d/0 e 0 e/1 f 0 --------------------- (LbÇ-La)Èf/1 = b/1, f/1 g 1 --------------------- --------------------- LfÈLcÈg/0 = b/1, f1, c/1, g/0 h 0 --------------------- (Lc-Ld)Èh/1 = c/1,h/1 i 0 --------------------- --------------------- LhÈLeÈi/1 = c/1,e/1, i/1, h/1 u 1 --------------------- --------------------- --------------------- Lg-LiÈu/0 = b/1, f1, g/0, u/0 So Lu = (Lg – Li) È u/0 = ((b/1, f/1, c/1, g/0) -(c/1)) + u/0= b/1, f/1, g/0, u/0, as indicated in the last column g f c G5 u=1 i=0 c=0 h=0 h=0 i=0 G3 G4 d=1 È È i/1 L =L L i h e e=0 Lh = - )È (L L h/1 c d Deductive Simulation

  20. Example of Deductive Simulation • Consider 3 faults: B/1, F/0, and J/0 and test t1={1,0,1} A 1 G 0 C x 1 x D B E J H x 1 F LB = {B/1}, LF = {F/0}, LA = Ø LC=LD = {B/1}

  21. Example of Deductive Simulation • Consider 3 faults: B/1, F/0, and J/0 A 1 G 0 C x 1 x D B E J H x 1 F LB = {B/1}, LF = {F/0}, LC=LD = {B/1}, LG = {B/1}, LE = {B/1}

  22. Example of Deductive Simulation • Consider 3 faults: B/1, F/0, and J/0 A 1 G 0 C x 1 x D B E 1 J H x 1 F LB = {B/1}, LF = {F/0}, LC=LD = {B/1}, LG = {B/1}, LE = {B/1}, LH = {B/1, F/0}

  23. Example of Deductive Simulation • Consider 3 faults: B/1, F/0, and J/0 A 1 G 0 0 C x 1 x D B E 1 J H 1 x 1 F LB = {B/1}, LF = {F/0}, LC=LD = {B/1}, LG = {B/1}, LE = {B/1}, LH = {B/1,F/0}, LJ = {F/0,J/0}

  24. Example of Deductive Simulation • When A changes from 1 to 0 A 0 G 0 0 C x 1 x D B E 1 J H 1 x 1 F LB = {B/1}, LF = {F/0}, LC=LD = {B/1}, LG = Ø, different set for t2={0,0,1} LE = {B/1}, LH = {B/1,F/0}, LJ = {B/1,F/0,J/0}

  25. 0 0 1 1 0 a b c d e f 0 j 0 i 1 1 m g h 1 k Deductive fault simulation Example : After fault collapsing, the set of faults we simulate is { a0, a1, b1, c0, c1, d1, e0, g0 , h0, h1} Perform deductive fault simulation using test vector t1={00110}

  26. x=1 x=1 x=0 x=1 x=1 y=0 y=0 y=1 y=0 y=0 z=0 - È - Ç - L (L L ) L L È L L L L L L x y z y x y x x y x y Deductive fault simulation Fault list { a0, a1, b1, c0, c1, d1, e0, g0 , h0, h1} a b c d e j 0 i 1 0 0 1 1 0 0 f g h 1 m 1 k Assume the first applied test vector is t1={00110} La = {a1}, Lb = {b1}, Lc = {c0}, Ld =  , Le =  , Lf = LaLb = , Lg = Lc {g0}={c0,g0}, Lh = Lc {h0}= {c0, h0}, Lj = Lg -Lf = {c0, g0}, Li = Ld Lh = {c0, h0}, Lk = Li -Le = {c0, h0}, Lm = Lk- Lj = {h0} Ç

  27. 1 1 0 1 0 a b c d e 1 f 0 j 0 i 0 m g h 0 k Example Using test vector t2={1,1,0,1,0} Fault list after fault collapsing { a0, a1, b1, c0, c1, d1, e0, g0 , h0, h1} Start with La = {a0}, Lb = , Lc = {c1}, Ld = , Le = 

  28. Deductive Fault list Faults detected in this step of deductive simulation La = {a0}, Lb = , Lc = {c1} Ld = , Le =  Lf = La  Lb = {a0} Lg = Lc = {c1} Lh = Lc  {h1} = {c1,, h1} Li = Lh - Ld = {c1,, h1} Lj = Lf - Lg = {a0} Lk = Li  Lg= {c1,, h1} Lm = Lj  Lk= {a0 ,c1, h1}

  29. Concurrent Fault Simulation • Each gate retains a list of fault copies and each of them stores the status of a fault different from fault-free values. • Simulation is similar to the regular fault simulation except that only the difference w.r.t. fault-free circuit is retained. • Very versatile in circuit types and gate delays • Although theoretically all faults in a circuit can be processed in one pass, memory explosion restricts the fault number in each pass.

  30. 1 0 0 0 0 1 0 1 0 Fault List of AND Gate A 0 D 0 B 0 A/1 faults B/1 D/1

  31. a0 c0 e0 b0 1 0 1 1 0 0 0 0 0 0 1 1 1 a 1 1 1 1 e 1 b 1 1 c 1 g 0 0 1 0 e0 a0 c0 b0 f d 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 1 1 0 1 0 0 1 1 1 b0 d0 g0 f1 f1 d0 Concurrent Fault Simulation

  32. D A 0 E 0 0 B 0 0 C 0 D A 1 E 0 0 B 0 0 C 0 Fault List Propagation A/1: 10_0 C/1: 01_1 B/1: 01_0 D/1: 10_1 D/1: 00_1 E/1: 00_1 Inputs and output faults * *A/0: 00_0 *B/1: 10_1 E/1: 00_1 *B/1: 11_1 C/1: 01_1 *D/1: 10_1 D/1: 10_1

  33. Example of Concurrent Simulation • Consider 3 faults: B/1, F/0, and J/0 A 1 G 0 C x 1 E x D B H J x 1 F signal LG = {10_0, B/1:11_1} LE = {0_1, B/1:1_0} Fault: Faulty inputs_output Inputs_output

  34. Example of Concurrent Simulation • Consider 3 faults: B/1, F/0, and J/0 A 1 G 0 C x 1 E 1 x D B H J x 1 F LG = {10_0, B/1:11_1} LE = {0_1, B/1:1_0} LH = {11_1, B/1:01_0, F/0:10_0}

  35. Example of Concurrent Simulation • Consider 3 faults: B/1, F/0, and J/0 A 1 G 0 0 C x 1 E 1 x D B H 1 J x 1 F LG = {10_0, B/1:11_1} LE = {0_1, B/1:1_0} LH = {11_1, B/1:01_0, F/0:10_0} LJ = {01_1, B/1:10_1, F/0:00_0, J/0:01_0}

  36. Example of Concurrent Simulation • When A changes from 1 to 0 A 0 G 0 0 C x 1 E 1 x D B H 1 J x 1 F LG = {00_0, B/1:01_0} LE = {0_1, B/1:1_0} LH = {11_1, B/1:01_0, F/0:10_0} LJ = {01_1, B/1:00_0, F/0:00_0, J/0:01_0}

  37. Gates and their inputs G2 G1 a b f c f g G3 c d h G4 e h i G5 g I u 1 0 0 0 0 1 0 1 0 0 0 0 1 0 1 a/0 0 0 0 b/1 0 1 0 c/1 1 1 1 c/1 0 1 1 b/1 0 0 0 b/1 1 1 1 c1/1 1 0 0 d/0 0 0 0 e/1 1 0 1 c/1 0 1 1 f f/1 1 0 1 /1 0 1 0 h/1 0 1 1 h/1 0 1 1 e/1 1 1 1 Detectable faults in bold f g/0 0 0 0 i/1 0 0 1 /1 0 0 0 g/0 0 0 0 h/1 1 1 1 i/1 1 1 1 u/0 1 0 0 Concurrent Simulation Possible faults Faulty responses

  38. Fault Simulation Exercise Unused output B faults not detected Tied to ground

More Related