Download
1 / 8
90 likes | 185 Views
Model based Design : a firmware perspective. …yes, including the CASPER tool-flow. Raj Thilak Rajan rajan@astron.nl ASTRON. Raj Thilak Rajan Uni-Board FP7 Kickoff meeting Friday, February 27, 2009. Legacy+ IP cores. Specifications. Manual Coding. Verification. FPGA. RTL Synthesis.
E N D
Model based Design : a firmware perspective …yes, including the CASPER tool-flow. Raj Thilak Rajan rajan@astron.nl ASTRON Raj Thilak RajanUni-Board FP7 Kickoff meetingFriday, February 27, 2009
Legacy+ IP cores Specifications Manual Coding Verification FPGA RTL Synthesis HDL Code ASIC Raj Thilak RajanUni-Board FP7 Kickoff meetingFriday, February 27, 2009 Traditional Firmware Development • Manual Coding • Time : arguably 40% (or more) of project timeline • Translation prone to errors • Verification • does not quantify the difference between input specifications and final system, for all scenarios.
Legacy+ IP cores Reference Model Co-Simulation FPGA ESL Synthesis RTL Synthesis HDL Code ASIC Raj Thilak RajanUni-Board FP7 Kickoff meetingFriday, February 27, 2009 Model based Design approach • Reference Model • Input specifications + High Level Modeling => Executable Specifications • Electronic System Level (ESL) synthesis • Automated translation • Co-Simulation • Verification with Reference Model
ESL synthesis Raj Thilak RajanUni-Board FP7 Kickoff meetingFriday, February 27, 2009 Framework… SIMULINK • Reference Model • SIMULINK • ESL synthesis tool • a plug-in • Libraries + HDL Generation • Only these libraries can be synthesized to HDL !
Xilinx FPGA Only Xilinx and Altera FPGA Altera FPGA Only Raj Thilak RajanUni-Board FP7 Kickoff meetingFriday, February 27, 2009 Available tools… • Inter-dependence • Reference Model < > ESL synthesis Tool • FPGA dependence • 3 Basic Tool Flows : Xilinx , Altera and Generic • Co-simulation • MathWorks SIMULINK based EDA Co-Simulator for Model-Sim, Discovery and Incisive • ESL Synthesis and Co-Simulation Independent
Raj Thilak RajanUni-Board FP7 Kickoff meetingFriday, February 27, 2009 CASPER – MSSGE • MSSGE : Matlab/Simulink/System Generator/ EDK tool-flow • Xilinx ONLY • MSSGE 10.1 libraries • CASPER DSP (50) • Communication (2) • System Blocks (8) • CASPER currently porting MSSGE libraries to Xilinx version 10.1
Raj Thilak RajanUni-Board FP7 Kickoff meetingFriday, February 27, 2009 CAPER MSSGE : Pros and Cons • • Save time and resources • Xilinx (90+) + MSSGE(50) => 140+ reusable blocks available • Initial firmware development time reduced • Efficiency • CASPER -> XSG -> best use of Xilinx FPGA resources • • Xilinx dependence • Xilinx ONLY blocks • Models cannot be ported to other ESL synthesis environments • Xilinx Version dependence • Stable : Xilinx 7.1 • Under Development : Xilinx 10.1 • Work arounds costing precious time… • Control and Communication • board specific blocks (20+) need to be developed • Long run : firmware development bound to Xilinx IP?
Raj Thilak RajanUni-Board FP7 Kickoff meetingFriday, February 27, 2009 Conclusion • Model based Design • Next level of abstraction • Single click - hardware implementation simplified • Caution: Tools not yet standardized for ESL synthesis ! • in contrast to VHDL for RTL synthesis • Tools • Co- simulation : flexible. • ESL synthesis : ? ? ? • Next Step • Investigate alternative generic tool flows • Mathworks : HDL Coder • Synopsys : Synplicity DSP • Need for hybrid tool-flow • Model based Design < > Traditional Development
