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MICE Readout DFPGA Firmware Progress

MICE Readout DFPGA Firmware Progress.  Bottom up work was carried out on the top level presentation of 07.11.06  Incremental design to ease the pain of debugging  Trip-t  DFPGA  AFPGA Discriminator bit map transfer control done and simulated

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MICE Readout DFPGA Firmware Progress

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  1. MICE Readout DFPGA Firmware Progress  Bottom up work was carried out on the top level presentation of 07.11.06  Incremental design to ease the pain of debugging  Trip-t  DFPGA  AFPGA Discriminator bit map transfer control done and simulated Reading Trip-t Discriminator Bit map into DFPGA FIFO with Depth control Down loading the Discriminator Bit map into D-A interface FIFO on Digitise  Add Xilinx Core Generated components Simulate  Add pin configuration Simulate  Test  Implement L1 Data Readout

  2. Trip-t Interface MapFIFO0UMSB MapFIFO0ULSB Disc 0 map 16 bit MapFIFO0LMSB MapFIFO0LLSB D-A FPGA Interface DIGEN0[ U/L/B] PRE-RST M U X Trip-t Interface MODE CTRL TxFIFO-D 8 bit 16 ->1 Read Select U/L Write DIGEN3[ U/L/B] MapFIFO3UMSB MapFIFO3ULSB Disc 3 map 16 bit MapFIFO3LMSB MapFIFO3LLSB

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