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Computer Architecture Chapter 2 Instructions: Language of the Computer

Computer Architecture Chapter 2 Instructions: Language of the Computer. Yu-Lun Kuo 郭育倫 Department of Computer Science and Information Engineering Tunghai University, Taichung, Taiwan R.O.C. sscc6991@gmail.com http://www.csie.ntu.edu.tw/~d95037/. Introduction.

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Computer Architecture Chapter 2 Instructions: Language of the Computer

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  1. Computer ArchitectureChapter 2Instructions: Language of the Computer Yu-Lun Kuo 郭育倫 Department of Computer Science and Information Engineering Tunghai University, Taichung, Taiwan R.O.C. sscc6991@gmail.com http://www.csie.ntu.edu.tw/~d95037/

  2. Introduction • Computer designers have a common goal • Find a language that makes it easy to build hardware and the compiler • Maximizing performance and minimizing cost • Instruction Set • Language of the machine, its vocabulary is called an instruction set • The vocabulary of commands understood by a given architecture.

  3. Introduction • We’ll be working with the MIPS instruction set architecture • Similar to other architectures developed since the 1980's • Almost 100 million MIPS processors manufactured in 2002 • Used by NEC, Nintendo, Cisco, Silicon Graphics, and Sony. • Stored-program concept • The idea that instructions and data of many types can be stored in memory as numbers, leading to the stored program computer.

  4. CPU Manufacturer (1/2) • Intel: Pentium IV, IA-64, i3, i5, i7 • AMD: K6-3, K7, Duron, Athron • IBM: PowerPC • Sun: SPARC • HP: PA-RISK, IA-64 • DEC: Alpha • MIPS: MIPS (Book) • VIA/Cyrix: C7 series • Motorola: DragonBall • Used in Palm handheld devices

  5. CPU Manufacturer (2/2)

  6. RISC (Reduced Instruction Set Computer) • RISC philosophy • fixed instruction lengths • load-store instruction sets • limited addressing modes • limited operations • Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them Design goals: speed, cost (design, fabrication, test, packaging), size, power consumption, reliability, memory space

  7. MIPS Instruction Set Architecture (ISA) R format OP rs rd sa funct rt I format OP rs rt immediate J format OP jump target 3 Instruction Formats: all 32 bits wide • Instruction Categories • Computational • Load/Store • Jump and Branch • Floating Point • Memory Management • Special Registers R0 - R31 PC HI LO

  8. MIPS arithmetic • HLL  MIPS Assembly  MIPS Machine • High Level Language Statements  Assembly Language Translation • The translation process includes • Assigning variables in high level language statement into registers • Translation into assembly

  9. Operations of MIPS • All instructions have 3 operands • Operand order is fixed (destination first) Example: C code: a = b + c; MIPS code: add a, b, c

  10. MIPS Arithmetic Instructions • MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 • Each arithmetic instruction performs only one operation • Each arithmetic instruction fits in 32 bits and specifies exactly three operands destination  source1 op source2 • Operand order is fixed (destination first)

  11. Operations of MIPS • Of course this complicates some things... C code: a = b + c + d; MIPS code: add a, b, c add a, a, d • Operands must be registers • Only 32 registers provided. (MIPS) • Each register contains 32 bits. (32bits = 4bytes = word)

  12. Example • Place the sum of variables b, c, d, and e into variable a add a, b, c add a, a, d add a, a, e # a = b+c+d+e; • Takes three instructions to take sum of four variables • # is comments for the human reader

  13. Operands of MIPS • All instructions have 3 operands • “The natural number of operands for an operation like addition is three…requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple” • Each line of this language can contain at most one instruction

  14. Operands of MIPS • Design Principle 1: Simplicity favors regularity • Simple  fixed number of operand  regularity Hardware for a variable number of operands is more complicated than hardware for a fixed number

  15. Compiling C into MIPS • C (Java) program contains the five variables a, b, c, d, and e a = b + c; d = a – e; • MIPS instruction

  16. Example Complex statement contains five variables f = (g + h) – (i + j); MIPS code: add t0, g, h #temporary add t1, i, j sub f, t0, t1

  17. Operands of MIPS • Design Principle 2: Smaller is faster. • A very large number of registers may increase the clock cycle time simply. • Because it takes electronic signalslonger when they must travel farther • Arithmetic instructions operands must be registers, only 32 registers are provided.

  18. Operands of MIPS (Registers) • Simply write instructions using numbers for register, from 0 to 31 • Following a dollar signto represent a register • Use $s0, $s1, … for registers that correspond to variables (variable registers) • Use $t0, $t1, … for temporary registers

  19. Example • Compiler’s job to associate program variables with registers f = (g + h) - (i + j); Variable f, g, h, i and j are assigned to the registers $ s0, $ s1, $ s2, $ s3, $ s4 add $t0,$s1,$s2 add $t1,$s3,$s4 sub $s0,$t0,$t1

  20. Registers vs. Memory Control Input Memory Datapath Output Processor I/O • The processor can keep only a small amount of data in registers, but computer memory contains millions of data elements

  21. Registers • Data is more useful in a register • MIPS registers take both less time to access and have higher throughput than memory • Faster to access • Highest performance • Simpler to use

  22. Memory Operands Store Memory Register load • Data transfer instructions • Arithmetic operations occur only on registers in MIPS, thus, MIPS must include instructions that transfer data between memory and registers. • Access a word in memory (supply memory address) • lw and sw • Addressing (定址) • A value used to delineate the location of a specific data element within a memory array.

  23. Memory Organization • Viewed as a large, single-dimension array, with an address. • A memory address is an index into the array • “Byte addressing” means that the index points to a byte of memory. ...

  24. Memory Organization • The constant in the data transfer instruction is called offset • The register added to form the address is called base register • Copy data from memory to register is called load • Register used to access memory • MIPS name for this instruction is lw • Standing for load word Base + offset offset Base address ($s3)

  25. Operand is in Memory (Example) • A is an array of 100 bytes • The variables g and h with registers $s1 and $s2 • The starting address (base address) of the array is in $s3 C code: g = h + A[8]; MIPS code: lw $t0, 8($s3) add $s1,$s2,$t0

  26. Memory Organization • Bytes are nice, but most data items use larger “words”, for MIPS, a word is 32 bits or 4 bytes. • 232 bytes with byte addresses from 0 to 232-1 • Words are aligned Alignment restriction 0 32 bits of data 4 32 bits of data 8 32 bits of data 12 32 bits of data ... Registers hold 32 bits of data

  27. Endian Problem little endian byte 0 3 2 1 0 msb lsb 0 1 2 3 big endian byte 0 • Since 8-bit bytes are so useful, most architectures address individual bytes in memory • The memory address of a word must be a multiple of 4 (alignment restriction) • Big Endian: leftmost byte is word address • IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA • Little Endian: rightmost byte is word address • Intel 80x86, DEC Vax, DEC Alpha (Windows NT)

  28. Compiling Using Load and Store • Load and store instructions C code: A[12] = h + A[8];MIPS code: lw $t0, 32($s3) add $t0, $s2 ,$t0 sw $t0, 48($s3) • Can refer to registers by name (e.g., $s2, $t0) instead of number • g$s1 register, h$s2 register • $s3 is Array A’s base register • Remember arithmetic operands are registers, not memory!Cannot write: add 48($s3), $s2, 32($s3) A[12] A[10] A[8] $s3 + 4*12 $s3 + 4*8

  29. Example • Example: • g$s1 register, h$s2 register, i $s4 • $s3 is Array A’s base register C code: g = h + A[i]; add $t1, $s4, $s4 add $t1, $t1, $t1 # $t1 gets 4*i add $t1, $t1, $s3 lw $t0, 0($t1)# $t0 gets A[i] lw $t0, $t1($s3) add $s1, $s2, $t0 A[i] A[0] $s3 + 4*i $s3

  30. Emphasis Store Memory Register load • Load: Memory  register (lw) • Store: register  memory (sw) Base+Offset Offset Base

  31. MIPS Register Convention Register 1 ($at) reserved for assembler, 26-27 for operating system

  32. Compiling Using Load and Store

  33. So far We Learn

  34. So far We Learn • Design Principle 3: Make the common case fast • MIPS • loading words but addressing bytes • arithmetic on registers only • Instruction Meaning add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 – $s3 lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1

  35. Spilling Register • Many programs have more variable than computers have registers • 32 registers in MIPS • Compiler tries to keep the most frequently used variables in registers and places the rest in memory • The process of putting less commonly used variables (needed later) into memory is called spilling registers

  36. Representing Instructions • Instructions, like registers and words of data, are also 32 bits long • Example: add $t1,$s1,$s2 • Registers have numbers (0, 1, 2, …, 31) • $s0 to $s7 map onto registers 16 to 23 • $t0 to $t7 map onto registers 8 to 15 • $t1=9, $s1=17, $s2=18 • Instruction Format:000000 10001 10010 01001 00000 100000 op rs rt rd shamt funct • Can you guess what the field names stand for? R format

  37. Representing Instructions 000000 10001 10010 01000 00000 100000 6-bit 5-bit 5-bit 5-bit 5-bit 6-bit • Binary representation • Instruction format • MIPS instructions are 32 bits long • Simplicity favors regularity

  38. Representing Instructions

  39. Representing Instructions

  40. MIPS Fields Arithmetic Instruction Format (R format) op rs rt rd shamt funct add $t0, $s1, $s2 op 6-bits opcode that specifies the operation rs 5-bits register file address of the first source operand rt 5-bits register file address of the second source operand rd 5-bits register file address of the result’s destination shamt 5-bits shift amount (for shift instructions) funct 6-bits function code augmenting the opcode 40

  41. Representing Instructions • Machine Language • Binary representation used for communication within a computer system • Instruction Format • A form of representation of an instruction composed of fields of binary numbers.

  42. MIPS Memory Access Instructions • MIPS has two basic data transfer instructions for accessing memory lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory • The load word instruction must specify two registers and a constant • Constant with the load word instruction would be limited to only 25 or 32 • 5 bit-field is too small to be useful (often much larger than 32)

  43. One Size Fits All? • The compromise chosen by the MIPS designer • Keep all instructions the same length • Requiring different kinds of instruction formats for different kinds of instruction • Design Principle 4: Good design demands good compromises • We have 3 types of instructions • R-type (register) • I-type (immediate) • J-type (jump)

  44. Representing Instructions

  45. Machine Language – Load Instruction op rs rt 16 bit offset • Load/Store Instruction Format (I format) • A 16-bit field meaning access is limited to memory locations within a region of 215 or 32,768 bytes (213 or 8,192 words) of the address in the base register • Note that the offset can be positive or negative lw $t0, 24 ($s2)

  46. MIPS Instruction Encoding

  47. Translate MIPS into Machine Language op rs rt address op rs rt rd shamt funct 0 18 8 8 0 32 35 43 9 9 8 8 1200 1200 op rs rt address • EX. $t1 has the base of array A, $s2 is h A[300] = h + A[300] complied into lw $t0, 1200($t1) add $t0, $s2, $t0 # $t0 gets h+A[300] sw $t0, 1200($t1)

  48. Translate MIPS into Machine Language • Binary representation op rs rt address 100011 01001 01000 0000 0100 1011 0000 op rs rt rd shamt funct 000000 10010 01000 01000 00000 100000 op rs rt address 101011 01001 0000 0100 1011 0000 01000

  49. So Far We Learn

  50. Stored Program Concept • Instructions are bits • Programs are stored in memory to be read or written just like data • Fetch and Execute Cycle • Instructions are fetched and put into a special register (Instruction Register) • Bits in the register “control” the subsequent actions • Fetch the “next” instruction and continue

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