Main Components Transmitting/Receiving Nodes: Four Xilinx Spartan IIE FPGAs

1. Reconfigurable Computing for Space Chris Canine, Cameron Dennis, Terseer Ityavyar Sponsored by Dr. Greg Donohoe, NASA, University of Idaho CAMBR • Purpose • Goal: • Provide a proof of concept design and documentation that highlight the benefits of using a low-voltage differential serial communications scheme rather than standard single-ended parallel interconnect. • Specifications: • Transfer data at a speed of 800 Mbps from either of two transmitting nodes to either of two receiving nodes • Show the stability of the system with a Bit Error Rate Test giving no errors in a 15 minute period. • Deliver documentation comparing serial differential signaling and parallel single-ended signaling on the basis of power consumption and circuit board area. The Product PCB Specifications Size: 12” W x 10.5” H Layers: Six w/ two planes Smallest Trace: 7 microns # of Components: 398 DC/DC Converters Provide efficient, point of use power conversion from +12V to required voltage. Includes enable and trim. LVDS Crossbar Retransmits incoming data to receiving FPGAs. Can act as splitter, repeater or crossover as needed. LCD Display Screen Allows the board to display the number of errors during the Bit Error Rate Test, or other information needed. Serializer/Deserializer Serializes 16-bit parallel data and clock into a serial stream at 1.25Gbps. Also recovers data at receiver. Decoupling Capacitors Provide quick, temporary energy during high power demand. Reduces effects of under-voltage situations. Spartan IIE FPGAs Generate the semi-random data used during the BERT and control the sending and receiving of data. Solution Low Voltage Differential Signaling (LVDS) A widely recognized standard which uses differential current direction to represent logic levels. This allows very high speed serial data to be sent through two 100 ohm matched impedance traces, using approx. 8 times less space than parallel signaling. Main Components Transmitting/Receiving Nodes: Four Xilinx Spartan IIE FPGAs Serializer/Deserializers: Four National DS92LV16’s LVDS Crossbar: One National SCAN90CP02 Power Supply: +12V Power Input Twelve Datel LSN DC/DC Converters Various Decoupling Capacitors • Pros • 350mV switching results in fewer power losses • Differential design creates little noise and rejects outside interference • Uses only two lines, no matter what the data transfer rate is • Cons • Matched impedance lines are more difficult to lay out when creating PCB • Requires that the components used support the standard and may require component changes Tx Rx 3.5mA + 350mV - 3.5mA Basic LVDS communication The team would like to thank the following people for their contributions and help: Dr. Joe Law, Dr. Herb Hess, Greg Klemesrud and John Geidl