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EEL 3705 / 3705L Digital Logic Design

EEL 3705 / 3705L Digital Logic Design. Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing Analysis (Thanks to Dr. Perry for some slides). Combinational Logic – Cost Analysis.

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EEL 3705 / 3705L Digital Logic Design

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  1. EEL 3705 / 3705LDigital Logic Design Fall 2006Instructor: Dr. Michael FrankModule #12: Combinational Logic Cost & Timing Analysis(Thanks to Dr. Perry for some slides)

  2. Combinational Logic – Cost Analysis • In practice, accurately calculating the manufacturing cost of a given design may be very complicated… • Some factors: • General type of logic technology used: • Custom VLSI vs. ASIC vs. FPGA vs. old-school TTL/MSI • Many precise details of the specific technology used • Nonlinear effects of wiring cost • Average wire length tends to grow as # of devices increases • Nonlinear effects of die area on IC yield • May be ameliorated by fault-tolerant architectural techniques • Still, a simple, first-order, back-of-the-envelope estimate of circuit cost can be obtained by modeling cost as linear in the number of gates or transistors used.

  3. Number of Transistors per Logic Gate • Example for a typical, simple static CMOS VLSI technology: • NOT gate (inverter) 2 transistors • Buffer 4 trans. • NAND/NOR: 4 T • AND/OR: 6 T • XOR/XNOR: 8-10 T • 8 if complement of input signal is already available

  4. Cost/Transistor Figures Today • Typical ballpark figures for a leading-edge, high-performance CPU with plenty of cache today (2007): • Cost per IC: ~$500 • Number of transistors: ~1 billion • Thus, the average cost per transistor is: • $500 / 109 T = $10−7/ T = 10−5 ¢/T = .00001 ¢/T • Note this includes an amortized share of the cost due to wiring, yield considerations, etc.

  5. Cost Estimation Example • Estimate the cost of a simple 64-bit ripple-carry adder in a modern VLSI process. • Half-adder = AND+XOR = 6+10 T = 16 T • Full adder = 2 HAs + OR = 2×16 + 6 = 38 T • 64 Full adders = 64 × 38T = 2,432 Ts • 2,432 T × .00001¢/T = .02432 ¢ • Thus, a simple 64-bit adder costs about two one-hundredths of a cent to manufacture • This may also be further optimized

  6. Cost-performance Analysis • An important figure of merit for many digital systems is their cost-performance, meaning performance (operations performed per unit of time) per unit of manufacturing cost • A.k.a. cost-efficiency, hardware efficiency • Can be measured in e.g. ops/sec/$ • Example: Suppose the 64-bit adder of the previous slide can be clocked at 1 GHz. What is its cost-performance, in terms of 64-bit add operations? • (109 ops / sec /adder)/(0.024 ¢/adder)×(100¢/$)= 4.2 × 1012 ops/sec/$

  7. Power-performance Analysis • As power consumption becomes a dominant limiting factor on performance, power-performance (performance per unit power dissipated) becomes increasingly important. • A.k.a. (computational) energy efficiency • Measured in ops/sec/Watt, or ops/Joule • Example: Suppose each logic gate in the previous example consumes 1 fJ = 6,241 eV on each clock cycle. What then is its power-performance for 64-bit adds? • Number of logic gates in adder design: 5×64 = 320 • Energy dissipated per 64-bit add operation: • 320 × 6,241 eV = 2 MeV = 3.2 × 10−13 J • Power-performance: • 1/(3.2×10−13 J) = 1.95 × 1013 ops/Joule = 3.125×1012 ops/sec/Watt

  8. Cost vs. Power Example • Suppose that, using the technology of the previous examples, I wish to design a massively parallel 3D graphics processing unit (GPU) for a handheld videogame unit. In this GPU, most of the cost and power budget goes to 64-bit add ops. But it must cost no more than $50, and dissipate no more than 10 Watts of power. Which is the major limiting factor on performance: Hardware cost, or power? • Cost-limited performance on 64-bit add operations: • (4.2×1012 ops/s/$)×($50) = 210 T adds/sec • Power-limited performance on 64-bit add operations : • (3.125×1012 ops/s/W)×(10W) = 31.25 T adds/sec • Power is by far the dominant limiting factor!

  9. Timing Analysis for Combinational Logic

  10. Delay Time • Def: Time required for output signal Y to change due to change in input signal X • Up to now, we have assumed this delay time has been 0 seconds. t=0 t=0

  11. Delay Time • In a “real” circuit, it will take tp seconds for Y to change due to X t=0 t=tp tp is known as the propagation delay time

  12. Timing Diagram • We use a timing diagram to graphically represent this delay Horizontal axis = time axis Vertical axis = Logical level axis (Logic One or Logic Zero)

  13. Timing Diagram • We see a change in X at t=0 causes a change in Y at t=tp Horizontal axis = time axis Vertical axis = Logical level axis (Logic One or Logic Zero)

  14. Timing Diagram • We also see a change in X at t=T causes another change in Y at t=T+tp We see that logic circuit F causes a delay of tp seconds in the signal

  15. Simple Example – Not Gate Let tp=2 ns Where ns = nanosecond = 1x10-9 seconds 2ns

  16. Simple Example – 2 Not Gates Let tp=2 ns 4ns 2ns 2ns Total Delay = 2ns + 2ns = 4ns

  17. Simple Example – 2 Not Gates Notes: Time axis is shared among signals Logic levels (1 or 0) are implied, not shown

  18. Simple Example – 2 Not Gates Sometimes dashed vertical lines are added to aid reading diagram 2ns 2ns 2ns 2ns 2ns

  19. Where does this delay come from? Circuit Delay

  20. Circuit Delay • All electrical circuits have intrinsic resistance (R) and capacitance (C). Let’s analyze a simple RC circuit

  21. Circuit Delay – Simple RC Circuit Vin Vout Note:

  22. Circuit Delay – Example Vin Vout Let R=1ohm, C=1F, so that RC=1 second Time Delay is 0.7s or 700 ms for 0.5Vdd Time Delay is 2.3s for 0.9Vdd Time Delay is 4.6s for 0.99 Vdd

  23. How do we relate this to logic diagrams?

  24. Def: tplh tplh = low-to-high propagation delay time This is the time required for the output to rise from 0V to ½ VDD tplh

  25. Def: tphl Tphl = high-to-low propagation delay time This is the time required for the output to fall from Vdd to ½ VDD tphl

  26. Def: tp (propagation delay time) Let’s define tp = propagation delay time as This will be the “average” delay through the circuit

  27. Gate Delay – Simple RC Model Ideal gate with tp=0 delay RC network Tp=tp_not Equivalent model with Gate delay of tp_not Ideal gate with RC network

  28. Gate Delay - Example X 0 25ns 5ns Y tp_not 0 5ns 30ns We indicate tp on the gate

  29. Combinational Logic Delay Longest delay This circuit has multiple delay paths A-Y = 5ns+5ns+5ns=15ns B-Y = 5ns+5ns+5ns+5ns=20ns C-Y = 5ns+5ns+5ns=15ns D-Y = 5ns Shortest delay Longest delay = 20ns Shortest delay = 5ns

  30. Combinational Logic Delay Longest delay We’ll use the longest delay to represent the logic function F. Let’s call it Tcl for time, combinational logic Shortest delay Longest delay = 20ns

  31. Combinational Logic (CL) Cloud Model Tcl=20ns Tcl=20ns

  32. Logic Simulators Used to simulate the output response of a logic circuit.

  33. Logic Simulations • Three primary types • Circuit simulator (e.g. PSPICE) • “Exact” delay for each gate • Most accurate timing analysis • Very slow compared to other types • Functional Simulation (e.g. Quartus ) • Assumes one unit delay for each gate • Very fast compared to other types • Most inaccurate timing analysis • Timing Simulation (e.g. Quartus) • Assumes “average” tp delay for each gate • Not the fastest or slowest timing analysis • Provides “pretty good” timing analysis

  34. TPS Quizzes

  35. Timing Quiz 1

  36. Calculate all delay paths through the circuit shown below What is the shortest and longest delay?

  37. Solution: Calculate all delay paths through the circuit shown below This circuit has multiple delay paths A-Y = 5ns+5ns+10ns=20ns B-Y = 2ns+5ns+5ns+10ns=22ns B-Y = 8ns+5ns+10ns=23ns C-Y = 8ns+5ns+10ns=23ns D-Y = 10ns Shortest path=10ns Longest path=23ns

  38. Timing Quiz 2

  39. Given the circuit below, find(a) Expression for the logic function(b) Longest delay in original circuit

  40. Solution: Given the circuit below, find(a) Original logic function(b) Longest delay in original circuit Longest Delay = 7ns+7ns = 14ns

  41. Timing Quiz 3

  42. Given the circuit below,(a) Using Boolean Algebra, minimize the logic function(b) Longest delay in minimized circuit Delay times are NOT gates= 2ns; AND,OR gates= 5ns NAND, NOR gates= 7ns; XOR gates: 10ns XNOR gates: 12ns

  43. Solution: Given the circuit below, find(a) Minimized logic function(b) Longest delay in minimized circuit Delay times are NOT gates= 2ns; AND,OR gates= 5ns NAND, NOR gates= 7ns; XOR gates: 10ns XNOR gates: 12ns You can show

  44. Solution: Given the circuit below, find(a) Minimized logic function(b) Longest delay in minimized circuit Delay times are NOT gates= 2ns; AND,OR gates= 5ns NAND, NOR gates= 7ns; XOR gates: 10ns XNOR gates: 12ns Longest delay is 7ns

  45. Solution Expanded

  46. Given the circuit below,(a) Using a Truth Table and a K-map, minimize the logic function

  47. Solution • Do yourself!

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