ELEC 2200-002 Digital Logic Circuits Fall 2008 Sequential Circuits (Chapter 6)

1. ELEC 2200-002Digital Logic CircuitsFall 2008Sequential Circuits (Chapter 6) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC2200-002 Lecture 12

2. Combinational vs. Sequential • Combinational circuit: • Output is a function of input • No memory • Example: parallel adder • Sequential circuit: • Output is a function of input and something else stored in the circuit • Internal memory • Example: serial adder ELEC2200-002 Lecture 12

3. Parallel and Serial Adders 0 0 1 1 0 1 0 0 Four-bit Adder 0 0 1 1 0 1 1 1 S C One-bit Adder 0 1 1 1 0 1 1 1 time time One-bit memory Memory initialized to 0 (initial carry = 0) Time synchroniaztion of Inputs, output, memory (clock) ELEC2200-002 Lecture 12

4. Another Example of Sequential Circuit • Four-year degree program: • Student can be in four states (Fr, So, Jr, Sr) • One-bit yearly input, 1 (pass) or 0 (fail) • Output = 1 (degree completed), 0 (in progress) • State diagram: 0/0 0/0 0/0 0/0 Fr 1/0 So 1/0 Jr 1/0 Sr Initial state 1/1 ELEC2200-002 Lecture 12

5. State Table or Excitation Table Initial State: Fr ELEC2200-002 Lecture 12

6. State Table (Alternative Form) Next state/output Inputs 0 1 Fr So Jr Sr Present state ELEC2200-002 Lecture 12

7. When Is Circuit Not Combinational? • When the input does not completely control output. • For a logic circuit without feedback, input uniquely determines the output. • Examples of non-combinational (sequential) circuits: Toggling 0-1 0 or 1 1 or 0 Odd inversions Even inversions ELEC2200-002 Lecture 12

8. SR Latch: Basic Sequential Circuit • Feedback loop with even number of inversions (no oscillation?). • Output(s): two sets of logic values from the loop. • Inputs: • Control loop logic values • Set the loop in “store” state ELEC2200-002 Lecture 12

9. Adding Inputs to Feedback Loop S R Q Q ELEC2200-002 Lecture 12

10. NOR Set-Reset (SR) Latch S R Q Q S R Q Q Q Q S R Symbol used in Logic schematics Also drawn as ELEC2200-002 Lecture 12

11. States of Latch ELEC2200-002 Lecture 12

12. The “Set” State Loop is broken S = 1 R = 0 Q = 1 Q = 0 Behavior is combinational. ELEC2200-002 Lecture 12

13. The “Reset” State S = 0 R = 1 Q = 0 Q = 1 Loop is broken Behavior is combinational. ELEC2200-002 Lecture 12

14. The “Store” State S = 0 R = 0 Q = 1 Q = 0 Loop is activated; behavior is sequential. ELEC2200-002 Lecture 12

15. The “Illegal” State S = 1 R = 1 Q = 0 Q = 0 Loop is broken in two places and inconsistent values inserted. ELEC2200-002 Lecture 12

16. “Illegal” State Cannot Be Stored Assume two gates have equal delays. S = 1 → 0 R = 1 → 0 Q = 0 → 1 → 0 → 1 → . . . Q = 0 → 1 → 0 → 1 → . . . Output oscillates with a period of loop delay. For unequal gate delays, faster gate will settle to 1 and slower gate to 0. This is known as RACE CONDITION. ELEC2200-002 Lecture 12

17. Excitation Table of SR Latch ELEC2200-002 Lecture 12

18. Characteristic Equation for SR Latch • Next-state function: • Treat illegal states as don’t care • Minimize using Karnaugh map • Characteristic equation, Q* = S +RQ S Q R ELEC2200-002 Lecture 12

19. State Diagram of SR Latch SR = 10 SR = 0X SR = X0 Q = 0 Q = 1 SR = 01 ELEC2200-002 Lecture 12

20. Clocked SR Latch S CK R SR-latch Q Q ELEC2200-002 Lecture 12

21. Delay Latch or D-Latch D CK Q Q ELEC2200-002 Lecture 12

22. Setup and Hold Times of Latch • Signals are synchronized with respect to clock (CK). • Operation is level-sensitive: • CK = 1 allows data (D) to pass through • CK = 0 holds the value of Q, ignores data (D) • Setup time is the interval before the clock transition during which data (D) should be stable (not change). This will avoid any possible race condition. • Hold time is the interval after the clock transition during which data should not change. This will avoid data from latching incorrectly. ELEC2200-002 Lecture 12

23. Latch Inputs tp 1 0 D time ts th 1 0 CK time tr ELEC2200-002 Lecture 12

24. JK-Latch SR-latch J K Q Q Characteristic Equation, Q = JQ* + K Q* Where Q = present state, Q* = previous state ELEC2200-002 Lecture 12

25. T-Latch (Toggle Latch) SR-latch J K Q Q T Characteristic Equation, Q = TQ* + T Q* Where Q = present state, Q* = previous state ELEC2200-002 Lecture 12

26. Master-Slave D-Flip-Flop Master latch Slave latch D CK Q Q ELEC2200-002 Lecture 12

27. Master-Slave D-Flip-Flop • Uses two level-sensitive clocked D-latches. • Transfers data (D) with one clock period delay. • Operation is edge-triggered: • Negative edge-triggered, CK = 1→0, Q = D (previous slide) • Positive edge-triggered, CK = 0→1, Q = D ELEC2200-002 Lecture 12

28. Negative-Edge Triggered D-Flip-Flop Clock period, T Master open Slave closed Slave open Master closed CK D Triggering clock edge Hold time Setup time Data stable Data can change Data can change Time ELEC2200-002 Lecture 12

29. D-Flip-Flop With CLEAR CLR Master latch Slave latch D CK Q Q ELEC2200-002 Lecture 12

30. D-Flip-Flop With PRESET Master latch Slave latch D CK Q Q PRESET ELEC2200-002 Lecture 12

31. Symbols for Latch and D-Flip-Flops CK D Q (LATCH) Level sensitive Q (DFF) Pos. Edge Triggered Q (DFF) Neg. Edge Triggered Q D CK D CK Q D CK Q

32. Register (3-Bit Example) • Stores parallel data Parallel input D0 D1 D2 CLR CK CLR D Q CK CLR D Q CK CLR D Q CK Q0 Q1 Q2 Parallel output ELEC2200-002 Lecture 12

33. Shift Register (3-Bit Example) • Stores serial data (parallel output) • Delays data (serial output) CLR D Serial input CK Serial output CLR D Q CK CLR D Q CK CLR D Q CK Q0 Q1 Q2 Parallel output ELEC2200-002 Lecture 12