ELEC 2200-002 Digital Logic Circuits Fall 2015 Logic Synthesis (Chapters 2-5)

1. ELEC 2200-002Digital Logic CircuitsFall 2015Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC2200-002 Lecture 6

2. Logic Synthesis • Definition: To design a logic circuit such that it meets the specifications and can be economically manufactured: • Performance – meets delay specification, or has minimum delay. • Cost – uses minimum hardware, smallest chip area, smallest number of gates or transistors. • Power – meets power specification, or consumes minimum power. • Testablility – has no redundant (untestable) logic and is easily testable. ELEC2200-002 Lecture 6

3. Synthesis Procedure • Minimization – Obtain MSOP or MPOS. This is also known as two-level minimization because the result can be implemented as a two-level AND-OR or NAND-NAND or NOR-NOR circuit. • Technology mapping – Considering design requirements, transform the minimized form into one of the technologically realizable forms: • Programmable logic array (PLA) • Standard cell library • Field programmable gate array (FPGA) • Others . . . ELEC2200-002 Lecture 6

4. References on Synthesis • G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994. • S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, 1994. ELEC2200-002 Lecture 6

5. Programmable Logic Array (PLA) • A direct implementation of multi-output function as a two-level circuit in MOS technology. • PLA styles: • NAND-NAND • NOR-NOR • Textbook, Chapter 5. ELEC2200-002 Lecture 6

6. Example: Two-Output Function Need four products: P1, P2, P3, P4 F1 A F2 A D D C C B B ELEC2200-002 Lecture 6

7. Two-Level AND-OR Implementation • Also known as technology-independent circuit. INPUTS AND OR C P1 F1 P2 A P3 F2 B P4 D ELEC2200-002 Lecture 6

8. NAND-NAND Implementation INPUTS NAND NAND C F1 A F2 B D ELEC2200-002 Lecture 6

9. A NAND Gate in nMOS Technology VDD VDD VDD Enhancement load Depletion load XY XY XY X X X Y Y Y GND GND GND R. C. Jaeger and T, N. Blalock, Microelectronic Circuit Design, Boston: McGraw-Hill, 2008, Section 6.8.2. ELEC2200-002 Lecture 6

10. NAND-NAND PLA A B C D F1 F2 VDD VDD VDD VDD VDD VDD GND ELEC2200-002 Lecture 6

11. NAND-NAND PLA SCHEMATIC A B C D F1 F2 INPUTS OUTPUTS Transistors at cross-points AND-plane OR-plane ELEC2200-002 Lecture 6

12. Standard-Cell Design • Obtain two-level minimized form. • Map the design onto predesigned building blocks called standard cells (technology mapping). • Standard-cell library contains predesigned logic cells in the technology of manufacture. Examples of technology: • 90 nanometer CMOS • 65 nanometer CMOS • 45 nanometer CMOS • . . . • This is known as application-specific integrated circuit (ASIC). ELEC2200-002 Lecture 6

13. Technology Mapping • Find a common logic element, e.g., two-input NAND gate or inverter (one-input NAND). • MSOP is converted into NAND-NAND circuit. • Split larger input gates into two-input NAND gates and inverters. • Cover the circuit with standard cells, also split into two-input NAND gates and inverters (graph-matching). ELEC2200-002 Lecture 6

14. A Typical Cell Library S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill 1994, Section 7.7, pp. 185-198. ELEC2200-002 Lecture 6

15. NAND3 Cell in Transistors VDD Z ABC GND ELEC2200-002 Lecture 6

16. NAND3 Cell Graphs Directed Acyclic Graph (DAG) (tree) Root ≡ Output One-input node (NOT) Two-input node (NAND) ELEC2200-002 Lecture 6

17. NAND4 Cell ELEC2200-002 Lecture 6

18. AOI21 Cell ELEC2200-002 Lecture 6

19. OAI21 Cell ELEC2200-002 Lecture 6

20. AOI22 Cell in Transistors VDD Pull-up network Pull-down network A B C D Z GND Observe that in a CMOS circuit, any vector of input variables connects the output Z either to GND or to VDD, giving it a value 0 or 1, respectively. Examining the pull-down network, we notice that the output is connected to GND if AB = 1 or CD =1. That gives the output function as, . The cell, therefore, is AOI22. ELEC2200-002 Lecture 6

21. AOI22 Cell ELEC2200-002 Lecture 6

22. XOR Cell ELEC2200-002 Lecture 6

23. NAND Graphs for Library Cells ELEC2200-002 Lecture 6

24. Technology Mapping Procedure • Obtain MSOP. • Convert to two-level AND-OR circuit. • Transform to two-level NAND-NAND circuit. • Transform to two-input NAND and inverter tree network. • Perform an optimal pattern matching to obtain a minimum cost tree covering. ELEC2200-002 Lecture 6

25. Previous Example: 2-Level NAND(Slide 8) INPUTS NAND NAND C F1 A F2 B D ELEC2200-002 Lecture 6

26. A Simple Technology Mapping NAND2 (3) NAND2 (3) (2) C F1 D NAND3 (4) NAND3 (4) B (2) F2 NAND2 (3) A Cost = 24 NAND2 (3) ELEC2200-002 Lecture 6

27. Optimum Mapping: Convert NAND Circuit to Directed Acyclic Graph (DAG) C F1 A F2 B Each node is a NAND gate. (NOT ≡ 1-input NAND) D ELEC2200-002 Lecture 6

28. Split DAG into Trees (Forest) C D F1 C B D A B F2 A D Cost = 24 ELEC2200-002 Lecture 6

29. Split Nodes With More Than Two Branches(Use NAND3, NAND4 Graphs) ≡ or F2 or F2 or ≡ NAND4 ELEC2200-002 Lecture 6

30. Uniform Branching (1 or 2) C F1 D B D C A F2 B A Cost = 32 D ELEC2200-002 Lecture 6

31. Graph Matching C OAI21 (4) (2) D F1 Nodes inserted For pattern matching B NAND3 (4) C D NAND3 (4) NAND2 (3) A F2 B (2) A D NAND2 (3) Cost = 22 ELEC2200-002 Lecture 6

32. Technology Mapping C OAI21 (4) D F1 (2) (2) Inverters inserted For pattern matching B NAND3 (4) C D NAND3 (4) A F2 B (2) NAND2 (3) A Cost = 22 D NAND2 (3) ELEC2200-002 Lecture 6

33. Mapped Circuit C AOI21 (4) F1 (2) D NAND3 (4) NAND3 (4) B (2) F2 NAND2 (3) A Cost = 22 NAND2 (3) ELEC2200-002 Lecture 6

34. Original Reference • K. Keutzer, “DAGON: Technology Binding and Local Optimization by DAG matching,” Proc.24th Design Automation Conf., 1987, pp. 341-347. ELEC2200-002 Lecture 6