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Handshake protocols for de-synchronization

Handshake protocols for de-synchronization. I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin and C. Sotiriou. Politecnico di Torino, Italy Universitat Politecnica de Catalunya, Barcelona, Spain Cadence Berkeley Lab, Berkeley, USA ICS-FORTH, Crete, Greece.

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Handshake protocols for de-synchronization

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  1. Handshake protocolsfor de-synchronization I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin and C. Sotiriou Politecnico di Torino, Italy Universitat Politecnica de Catalunya, Barcelona, Spain Cadence Berkeley Lab, Berkeley, USA ICS-FORTH, Crete, Greece

  2. Asynchronousfor dummies I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin and C. Sotiriou Politecnico di Torino, Italy Universitat Politecnica de Catalunya, Barcelona, Spain Cadence Berkeley Lab, Berkeley, USA ICS-FORTH, Crete, Greece

  3. Outline • What is de-synchronization ? • Behavioral equivalence • 4-phase protocols for de-synchronization • Concurrency • Correctness • An example

  4. De-synchronize Asynchronous CLK Synchronous CLK

  5. MS flip-flop Synchronous circuit L L L L 0 1 0 1 CLK 0 0 L L

  6. C C C C C C De-synchronization L L L L 0 1 0 1 0 0 L L

  7. De-synchronization Distributed controllers substitute the clock network C C C C C C The data path remains intact !

  8. Design flow • Think synchronous • Design synchronous:one clock and edge-triggered flip-flops • De-synchronize (automatically) • Run it asynchronously

  9. Prior work • Micropipelines (Sutherland, 1989) • Local generation of clocks • Varshavsky et al., 1995 • Kol and Ginosar, 1996 • Theseus Logic (Ligthart et al., 2000) • Commercial HDL synthesis tools • Direct translation and special registers • Phased logic (Linder and Harden, 1996) (Reese, Thornton, Traver, 2003) • Conceptually similar • Different handshake protocol (2 phase vs. 4 phase)

  10. Automatic de-synchronization • Devise an automaticmethod forde-synchronization • Identify a subclass of synchronous circuits suitable for de-synchronization • Formally prove correctness

  11. Outline • What is de-synchronization ? • Behavioral equivalence • 4-phase protocols for de-synchronization • Concurrency • Correctness • An example

  12. Synchronous flow

  13. De-synchronized flow

  14. +

  15. Flow equivalence [Guernic, Talpin, Lann, 2003]

  16. A B

  17. Flow equivalence CLK A 1 3 0 2 1 5 3 1 6 0 B 5 1 2 3 1 4 2 4 3 1 Synchronous behavior A 1 3 0 2 1 5 3 1 6 0 B 5 1 2 3 1 4 2 4 3 1 De-synchronized behavior

  18. Flow equivalence CLK A 1 3 0 2 1 5 3 1 6 0 B 5 1 2 3 1 4 2 4 3 1 Synchronous behavior A 1 3 0 2 1 5 3 1 6 0 B 5 1 2 3 1 4 2 4 3 1 De-synchronized behavior

  19. Outline • What is de-synchronization ? • Behavioral equivalence • 4-phase protocols for de-synchronization • Concurrency • Correctness • An example

  20. C C C C C C L L L L 0 1 0 1 0 0 L L

  21. C C C C C C

  22. L C

  23. A+ B- C+ D- A- B+ C- D+ A+ B- C+ D- A- B+ C- D+ A+ B- C+ D- A latch cannot read another data item untilthe successor has captured the current one A B C D 0 0 0 0

  24. A+ B- C+ D- A- B+ C- D+ A+ B- C+ D- A- B+ C- D+ A+ B- C+ D- A latch cannot read another data item untilthe successor has captured the current one A B C D 0 1 0 0

  25. A+ B- C+ D- A- B+ C- D+ A+ B- C+ D- A- B+ C- D+ A+ B- C+ D- A latch cannot read another data item untilthe successor has captured the current one A B C D 0 0 0 0

  26. A+ B- C+ D- A- B+ C- D+ A+ B- C+ D- A- B+ C- D+ A+ B- C+ D- A B C D 1 0 0 0 A latch cannot read another data item untilthe successor has captured the current one

  27. A+ B- C+ D- A- B+ C- D+ A+ B- C+ D- A- B+ C- D+ A+ B- C+ D- A B C D 0 0 0 0

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