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DPU PRESENTATION

DPU PRESENTATION. R.Orfei & S. Pezzuto CNR- IFSI. Design status (1/2). Design Completed for the HW boards (contracted to Carlo Gavazzi Space): - CPU Board - I/F Board - DC/DC Converter Board - Motherboard First set of boards delivered beginning of November 2000

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DPU PRESENTATION

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  1. DPU PRESENTATION R.Orfei & S. Pezzuto CNR- IFSI Digital Processing Unit

  2. Design status (1/2) • Design Completed for the HW boards (contracted to Carlo Gavazzi Space): - CPU Board - I/F Board - DC/DC Converter Board - Motherboard • First set of boards delivered beginning of November 2000 • DC/DC Converter to be delivered on 25-2-’02 Digital Processing Unit

  3. DESIGN STATUS (2/2) • Cabling between Motherboard and Front Wall Connectors finished • Design and manufacture of the box finished • AVM SW: S/C IF (nominal mode): 100% (burst mode): under testing Controller: 100% HK monitoring: 100% Procedure handling: 100% (coding single proc.) 1355 I/F: porting drivers under VIRTUOSO Digital Processing Unit

  4. OBS ARCHITECTURE DESIGN Digital Processing Unit

  5. BUDGETS FOR FM (1/2)(ACTUAL MASS INFERRED FROM AVM BOARDS) • Box weight (mechanics): 3037 g CPU Boards (2 of): 960 g I/F Boards (2 of): 640 g DC/DC Boards (2 of) (E): 1000 g Motherboard: 520 g Screws etc.: 100 g Cabling (E): 300 g Conformal coating (E): 420 g TOTAL (E) 6977 g (+-200 g) Digital Processing Unit

  6. BOX INTERFACE CONTROL DRAWING Digital Processing Unit

  7. BUDGETS FOR FM (2/2) TOTAL ESTIMATED POWER (DC/DC CONVERTER EFFICIENCY = 70%): 14.6 W Digital Processing Unit

  8. JTAG DSP 21020 RAM 1355 MEZZANINE FPGA EPROM 20 MHz CPU BOARD Digital Processing Unit

  9. FIFOS FIFOS S/S I/Fs A/D Conv. 16 MHz 1553B (S/C I/F) Long Stub Trafos “A” and “B” FPGA I/F BOARD Digital Processing Unit

  10. ICE Computer Monitor Power Supplies JTAG In Circuit Emulator (ICE) Motherboard CPU+I/F+Motherboard assembled during preliminary tests at CGS Digital Processing Unit

  11. AIV FLOW Digital Processing Unit

  12. SCHEDULES (1/4) Digital Processing Unit

  13. SCHEDULES (2/4) Digital Processing Unit

  14. SCHEDULES (3/4) Digital Processing Unit

  15. SCHEDULES (4/4) Digital Processing Unit

  16. PA/QA ACTIVITIES • ALL COMPONENTS ARE BOUGHT THROUGH THE CO-ORDINATED PARTS PROCUREMENT AGENCY • FOR INDUCTORS AND TRANSFORMERS RELEVANT RFAs AND PADs ARE ISSUED • NO RE-FLOW SOLDERING IS FORESEEN: ALL HAND MADE SOLDERS BY ESA QUALIFIED PERSONNEL • ENVIRONMENTAL QUALIFICATION TESTS ARE SCHEDULED FOR QM UNITS • ENVIRONMENTAL ACCEPTANCE TESTS ARE SCHEDULED FOR FM UNITS Digital Processing Unit

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