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Survey of Programmable Video Signal Processors

Survey of Programmable Video Signal Processors. CET-520. Kshipra Bopardikar. Agenda. Digital Multimedia Applications Explanation of MPEG Concepts Discussion of Algorithms used MPEG Encoder PVSP architecture proposed in Paper 1 (1989) PVSP architecture proposed in Paper 2 (2002)

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Survey of Programmable Video Signal Processors

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  1. Survey of Programmable Video Signal Processors CET-520 Kshipra Bopardikar

  2. Agenda • Digital Multimedia Applications • Explanation of MPEG Concepts • Discussion of Algorithms used • MPEG Encoder • PVSP architecture proposed in Paper 1 (1989) • PVSP architecture proposed in Paper 2 (2002) • Comparison • Conclusion

  3. Multimedia Applications • Entertainment • HDTV • Video on Demand (VoD) • Music (MP3) Sharing • Communication • Video Phone / 3G Mobile Phones • PDAs • Video Conferencing • Cameras • IP Cameras • Digital Camcorders • Other Fields • Image Processing • Robotics

  4. Traditional Microprocessor Limitations Modern multimedia applications are characterized by large amounts of data processing at a very high speed. Traditional general purpose Microprocessors are ill-suited for these applications because: • Logic overhead: Various Data types,Registers, Memory hierarchy, etc. are designed with desktop data processing in mind – not Video Signal Processing. • Unpredictability: Because of the complexity of logic, microprocessors can be unpredictable. • Speeds: In applications such as MPEG-4 encoding, over 50% of processor cycles may be spent evaluating one block of an algorithm (e.g. motion estimation, etc.). Hence there is a need for hardware implementation of these algorithms.

  5. What is a PVSP ? • Video Signal Processor (VSP) is a processor which is specifically designed to cater the needs of complex digital video signal computations. • P-VSP is programmable VSP. It is designed by abstracting a wide range of video processing algorithms that need to be supported.

  6. P-VSP Requirements Throughput Fast clock speed High parallelism High utilization Storage Large on-chip memory Large register file Efficient memory I/O Programmability

  7. MPEG Fundamentals • MPEG • A video stream is a sequence of video frames. Each frame is a still image. • Frames are divided into 16x16 pixel macro-blocks. • Macro-blocks are the units for motion-compensated compression.

  8. Motion Estimation/Compensation

  9. MPEG Encoder Architecture MPEG Signal Quantization Encoding Raw Video Signal DCT - Forward Path Motion Compensation from previous frame for data compression Inverse Quantization Motion Estimation Recover Original Image M.E. Output i.e. Motion Vector Inverse DCT M.C. Signal to Recover Image + Old Frame Information for M.E. Motion Compensation Frame Memory Old Frame Information for M.C.

  10. Video Processing Algorithms • Motion Estimation • Motion Compensation • Discrete Cosine Transform (DCT) • Inverse-DCT • Quantization / Inverse Quantization • Variable Length Coding (VLC) • Variable Length Decoding (VLD)

  11. Overview of Research Paper-1

  12. Chip Level Architecture

  13. Module Level Architecture

  14. Overview of Research Paper-2

  15. Algorithm Pipeline Stages Motion Estimation ID MR PALU TA ACC Motion Compensation ID MR PALU MW DCT ID MR PALU PMA0 PMA1 PMA2 MW Inverse DCT ID MR PMA0 PMA1 PMA2 PALU MW Quantization / Inverse Q. ID MR PMA0 PMA1 MW VLC IS SA ECO VLD CAD SM SR Paralleling Techniques in Research Paper 2: Pipelining

  16. Other Optimization Techniques in Research Paper 2: • Tree Adder • SIMD • PMA

  17. Comparison

  18. Conclusion • The architecture proposed in Research Paper-1 is over a decade old. • Research Paper 1 was proposed before the MPEG standards were formulated, and hence it does not address the specific requirements of the MPEG compression algorithms such as DCT, I-DCT. • It involves multiple VSP chips thus increasing cost. • Research paper 2 has strong advantages in price, size, state-of-the-art technology and usefulness.

  19. References • "Programmable parallel processor for video processing" by Takao Nishitani, Ichiro Tamitani and Hidenobu Harasaki • "A reconfigurable digital signal processor for high-efficiency MPEG-4 video encoding" • “MultiProcessor performance for Real-Time Processing of Video Coding Applications” By Peter Pirsch, Klaus Gaedke • "A general purpose video signal processor: architecture and programming" by Dijkstra, Essink, Hafkamp, den Hengst, Huizer, van Roermund, Sluyter and Snijder • Amphion MPEG-4 Video Encoder (CS6701) Preliminary Product Brief (http://www.amphion.com) • “Datapath Design for a VLIW Video Signal Processor” Presentation by Json Fritts (Princeton University) • “A Video Signal Processor for MIMD Multiprocessing” Presentation by Jorg Hilgenstock, Klaus Herrmann, Jan Otterstedt, Dirk Niggemeyer & Peter Pirsch (University of Hannover) • “MPEG Compression” Presentation from Xilinx. • “Array-of-Arrays Architecture for Parallel Floating Point Multiplication” by Dhanesha, Falakshahi and Horowitz, Stanford University • “A high performance low-power asynchronous matrix-vector multiplier for discrete cosine transform” by Kim and Beerel, University of Southern California

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