On the Selection of Efficient Arithmetic Additive Test Pattern Generators

On the Selection of Efficient Arithmetic Additive Test Pattern Generators S. Manich, L. García, L. Balado, E. Lupon, J. Rius, R. Rodriguez, J. Figueras Universitat Politècnica de Catalunya, UPC

Outline • Introduction • Motivation • State of the art • Objective • Proposed technique • Experimental results • Conclusions

System on Chip (external test access is difficult)

Moore’s Law for Test: Fab vs. Test Capital • SIA Roadmap Data 2001

Using BIST for DFT BIST e.g. LFSR’s

First proposed by Rajski and Tyszer. Similar LFSR behavior. Proved by Chiusano, Prinetto and Wunderlich Reusing internal datapaths DATAPATH Increment Test Pattern Generator Signature Analyzer Adder Accumulator Test Vectors

Comparison of test sequences 119 test vectors LFSR AdTPG

Comparison between LFSR and AdTPG • c3540, fault coverage of stuck-at. No reseeding AdTPG LFSR Fault coverage Test vector

Drawbacks of the AdTPG

Memory size doubles MEMORY MEMORY Seed 1 Seed 1 l1 l1 Increment 1 LFSR AdTPG

Memory size doubles MEMORY MEMORY Seed 1 Seed 1 l1 l1 l2 Seed 2 Increment 1 l2 Seed 2 Increment 2 LFSR AdTPG

Memory size doubles MEMORY MEMORY Seed 1 Seed 1 l1 l1 l2 Seed 2 Increment 1 l3 l2 Seed 3 Seed 2 Increment 2 Seed 3 l3 Increment 3 LFSR AdTPG

Memory size doubles MEMORY MEMORY SI triplet Seed 1 Seed 1 l1 l1 l2 Seed 2 Increment 1 l3 l2 Seed 3 Seed 2 l4 Seed 4 Increment 2 l3 Seed 3 Increment 3 Seed 4 l4 Increment 4 LFSR AdTPG

Generation period less than 2n 111...1 000...0 Seed 001...1 101...1 011...1

Generation period less than 2n 111...1 000...0 Increment 001...1 101...1 011...1

Generation period less than 2n 111...1 000...0 001...1 101...1 011...1

Unswitched input signals during test 119 test vectors LFSR AdTPG

Unswitched input signals during test 119 test vectors LFSR Shadow from 11...11 substring AdTPG Shadow from 00...01 substring

Proposed methodologyLUCSAM

DATAPATH Increment Adder Accumulator Test Vectors Using same value for seed and increment MEMORY SS triplet Seed 1 l1 l2 Seed 2 l3 Seed 3 l4 Seed 4 k-triplet set

Always generate odd increments Seed 1 Increment 1 LSB

Period of the test sequence is 2n 111...1 000...0 001...1 101...1 011...1

Avoid shadow zones in test sequence • Limit the size of substrings 11...11 or 00...01 • Rule of thumb: “Any input switchs at least one time” Increment 11.......11 00.......01 11.......11 00.......01 A (maximum subgroup size) T (test length)

Proposed methodology Procedurepreparation ofk-triplet setforcircuit C and a fault set  Define target FC* and initial lenght L Run ATPG(C,) to generate initial test set S (initial set of seeds) for target FC* WhileFC < FC*do For all seeds in S do Run HiFault(AdTPG(seed,seed’,L),C,) and calculateFC end do Select seed giving maximum FC increase Reduce set , set S and calculate length l Append in k-triplet set the SS triplet (seed,l) end do end procedure

Proposed methodology Fault Set Test Set ATPG Circuit

Proposed methodology Fault Set Fault simulator Test Set Test sequence AdTPG Seed1(l1)

Proposed methodology Fault Set Fault simulator Test Set Test sequence AdTPG Seed1 Seed1(l1) Seed2(l2)

Proposed methodology Fault Set Fault simulator Test Set Seed2 Test sequence AdTPG Seed1 Seed1(l1) Seed2(l2) Seed3(l3)

Proposed methodology Fault Set Fault simulator Test Set Seed2 Test sequence AdTPG Seed1 Seed1(l1) Seed2(l2) Seed3(l3) Seed4(l4) Seed3

k-triplet set Seed1(l1) Seed2(l2) Seed3(l3) Seed4(l4) Proposed methodology Fault Set Fault simulator Test Set Seed2 AdTPG Seed1 Seed4 Seed3

On the Selection of Efficient Arithmetic Additive Test Pattern Generators