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Hybrid Lithography Optimization with E-Beam and Immersion Processes for 16nm 1D Gridded Design

Hybrid Lithography Optimization with E-Beam and Immersion Processes for 16nm 1D Gridded Design. Y. Du, H. Zhang, M. D.F. Wong and K. Chao Dept. of ECE, University of Illinois at Urbana-Champaign. ASPDAC 2012. Outline. Introduction Process Overview Lithography Simulation Problem Formulation

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Hybrid Lithography Optimization with E-Beam and Immersion Processes for 16nm 1D Gridded Design

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  1. Hybrid Lithography Optimization with E-Beam and Immersion Processes for 16nm 1D Gridded Design Y. Du, H. Zhang, M. D.F. Wong and K. Chao Dept. of ECE, University of Illinois at Urbana-Champaign ASPDAC 2012

  2. Outline • Introduction • Process Overview • Lithography Simulation • Problem Formulation • ILP Formulation • Iterative Algorithm • Experimental Results • Conclusion

  3. Introduction • As the IC industry continues to shrink the technology node into sub-32nm, how to manufacture the randomly distributed cuts with reasonable throughput becomes a big challenge. • Hybrid lithography is to implement more than one types of lithography processes for a single layer manufacturing. • 193 nm immersion process • Electron beam (E-beam)

  4. Introduction • Immersion Process • Highly regular geometry patterns within resolution limit.

  5. Introduction • E-beam • Lower throughput but good for random complex patterns in a small amount.

  6. Introduction • The hybrid process for cut can be improved after cut redistribution. • How to maximize the cuts that can be printed by 193i and minimize the cuts for E-beam to increase the throughput becomes a challenging problem.

  7. Process Overview

  8. Lithography Simulation • The lithography simulation is performed on the cuts for 16nm 1D gridded design.

  9. Lithography Simulation • According to the region of forbidden patterns, two cuts with different vertical distances require different minimum horizontal distances to avoid forbidden patterns. • Unless two cuts connect each other either vertically or horizontally to create a bigger cut, they must be at least a safe distance away in order for qualified printing.

  10. Problem Formulation • If the cuts’ positions are not allowed to be changed, many of them will need EBL to print. • However, by proper wire end extension, the cuts can be redistributed to remove most forbidden patterns. • Problem definition: • Given a 1D layout with n gaps, where each gap is defined by two cuts on its two ends, cl and cr, and each cut can move within the gap it defines. • The objective is to remove the minimum number of cuts (print by EBL), and find the target locations for the remaining ones (print by 193i) with the least total wire extension, such that no forbidden pattern exists.

  11. ILP Formulation • Objective: • Where n is the total number of gaps, M is a big number, Si are binary variables, X2i and X2i-1 denote the x coordinates for the left and right cuts of gap i. • The primary objective is to minimize the number of cuts that should be printed by EBL. • The second objective is to minimize the total cuts’ moving distance from the original wire end positions.

  12. ILP Formulation X2 X1 l1 r1 gap 1 • Basic constraints: • li and ri denote the x coordinates for the left and right ends of gap i respectively. X2 X1 l1 r1 gap 1 S1=1 X1 X2 X2 X1 X2 X1 l1 r1 l1 r1 l1 r1 gap 1 gap 1 gap 1 S4=1 S3=1 S2=1

  13. ILP Formulation • Neighborhood constraints on overlapping gaps can be converted to dis-equality constraints: • N1: For two cuts Ci and Cj on the same track. • N2: For two cuts Ci and Cj whose vertical distance is 1.

  14. ILP Formulation • N3: For two cuts Ci and Cj whose vertical distance is 2 and another cut Ck whose vertical coordinate is between those of Ci and Cj.

  15. ILP Formulation • The dis-equality constraint X≠Y can be converted to the following three ILP constraints: • where B1 and B2 are additional binary variables and M is a big number.

  16. ILP Formulation • The conditional dis-equality constraint X≠Z → X ≠Y can be converted to the following three ILP constraints: • where B1, B2, B3 and B4 are additional binary variables and M is a big number.

  17. A few tracks are selected as target tracks in each iteration. The ILP solver is called to optimally find the cuts’ locations on the target tracks.

  18. Experimental Results

  19. Experimental Results

  20. Experimental Results

  21. Conclusion • This paper proposes a hybrid lithography process for advanced 1D gridded design, which involves 193i and EBL processes. • The optimal ILP algorithm reports optimal solutions for sparse layers, and the iterative algorithm is able to solve any size of dense layers efficiently.

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