1 / 45

Power PMAC ASIC Setup Elements November 2013

Power PMAC ASIC Setup Elements November 2013. Delta Tau Machine Interface ASICs. Custom digital ICs containing key machine-interface logic Designed by Delta Tau for each generation of controller Built by “silicon foundries” to Delta Tau specifications

fathi
Download Presentation

Power PMAC ASIC Setup Elements November 2013

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Power PMAC ASIC Setup ElementsNovember 2013

  2. Delta Tau Machine Interface ASICs • Custom digital ICs containing key machine-interface logic • Designed by Delta Tau for each generation of controller • Built by “silicon foundries” to Delta Tau specifications • Built using “gate array” technology – ICs are called “Gates” • Most UMAC accessory boards are built around one of these ICs • Almost all machine I/O information – servo and non-servo – passes through these ICs • ICs appear to CPU as sets of memory-mapped registers • Power PMAC provides data structure to access registers (and parts of registers) for each IC • Script language can access partial-word and whole-word elements • C language can access whole-word elements only (and thru API functions) – must mask and shift for partial-word components • Saved setup elements permit automatic software configuration of hardware interfaces

  3. PMAC2-Style ASICs • “DSPGATE1” PMAC2-style Servo IC • Used on ACC-24E2, ACC-24E2A, ACC-24E2S, ACC-51E boards • 4 channels servo interface circuitry – supports digital and analog interfaces • System clock generation circuitry • Power PMAC accesses with Gate1[i] data structure (or an alias) • “DSPGATE2” PMAC2-style MACRO IC • Used on ACC-5E board • 16 nodes of MACRO-ring I/O registers (4 in, 4 out per node) • 2 channels servo interface circuitry – supports digital and analog interfaces • 48 digital I/O points (most share pins with servo circuitry) • System clock generation circuitry • Power PMAC accesses with Gate2[i] data structure (or an alias) • “IOGATE” PMAC2-style Digital I/O IC • Used on ACC-14E, ACC-65E, ACC-66E, ACC-67E, ACC-68E boards • 48 digital I/O points, programmable direction and polarity • Power PMAC accesses with GateIo[i] data structure (or an alias)

  4. PMAC2-Style “DSPGATE1” Block Diagram • Appears to processor as 64 memory-mapped 24-bit registers • 4 global control registers • 15 registers per channel • Placed into high 24 bits of Power PMAC’s 32-bit data bus

  5. PMAC3-Style ASIC • “DSPGATE3” PMAC3-style Machine-Interface IC • Used on UMAC ACC-24E3 axis-interface board assemblies • Used on UMAC ACC-5E3 MACRO-interface board • Used in Power PMAC Etherlite network controller • Used in Power PMAC Brick boxed controller • Used in Power PMAC Clipper (upcoming) • Combines functionality of all PMAC2-style ASICs into one • Improves all aspects of functionality (speed, resolution, flexibility, etc.) • 4 channels servo interface circuitry – supports digital and analog interfaces • 4 banks 32 digital I/O points (3 banks share pins with servo channels) • 32 nodes of MACRO-ring I/O registers (4 in, 4 out per node) • System clock generation circuitry • Power PMAC accesses with Gate3[i] data structure (or an alias)

  6. PMAC3-Style “DSPGATE3” Block Diagram • Appears to processor as 512 memory-mapped 32-bit registers • 32 registers per servo channel • 8 multi-channel control registers • 16 GPIO registers • 256 MACRO data registers • 1st servo channel and 1st I/O bank have dedicated pins • 2nd – 4th servo channels and I/O banks share pins

  7. ASIC and Channel Index Values • Power PMAC can address multiple ASICs of each type • Each ASIC must have a unique hardware address in Power PMAC’s I/O space, usually set by DIP switches • Each ASIC has an index value (“i”) corresponding to hardware address • Gate1[i] index values range from 4 to 19 (0 to 3 reserved) • Power PMAC index i is twice comparable Turbo PMAC IC number m • Gate2[i] index values range from 0 to 15 • Gate3[i] index values range from 0 to 15 • GateIo[i] index values range from 0 to 15 • Address space shared with I/O boards that do not use this ASIC • Servo channel index values (“j”, e.g. Gate1[i].Chan[j].) correspond to hardware channels n • Channel index values j range from 0 to 3 • Hardware channel values n range from 1 to 4 • Channel index j corresponds to hardware channel n = j + 1

  8. ASIC Structure Name Aliases • ASIC data structure represents full software access to hardware containing the ASIC • Some users want to use hardware name in programs, not ASIC name • Can use “alias” name of hardware for data structure in Script • Feature not available in C (but can do #define text substitution) • Alias names for Gate1[i] • Acc24E2[i], Acc24E2A[i], Acc24E2S[i], Acc51E[i] • Alias name for Gate2[i] • Acc5E[i] • Alias names for Gate3[i] • Acc24E3[i], Acc5E3[i], Acc5EP3[i], Acc59E3[i], PowerBrick[i] • Alias names for GateIo[i] • Acc14E[i], Acc65E[i], Acc66E[i], Acc67E[i], Acc68E[i] • In alias name, index value i is the same as for IC name • Represents address within this class of hardware

  9. IDE Interactive Setup of ASIC Elements • From IDE “Delta Tau” menu, select “Configure”, then “Setup Variables” • Select desired hardware device (IC) from left section of pop-up window • Select component (e.g. channel) within IC/device • Select element from right section to view or modify

  10. Software configurable hardware signals • Limit on PWM up/down counter sets PWM and “MaxPhase” freq. • Phase clock freq. divided from MaxPhase • Servo clock freq. divided from Phase • Hardware clock freq. divided from 40 MHz

  11. PMAC2 Servo IC System Clock Elements • Gate1[i].PwmPeriod sets period of PWM cycle and of internal “MaxPhase” clock • MaxPhase frequency is twice PWM frequency • Gate1[i].PhaseClockDiv sets division of Phase clock from MaxPhase clock:fPhase = fMaxPhase / (PCD+1) • Gate1[i].ServoClockDiv sets division of Servo clock from Phase clock:fServo = fPhase / (SCD+1) • Gate1[i].PhaseServoDir = 0: Output both clocks = 3: Input both clocks

  12. PMAC2 IC Hardware Clock Signals • These control specific hardware functions of the IC • Encoder sample clock (SCLK) drives encoder input circuitry • Raise to permit higher count rate • Lower to provide more filtering of noise glitches • Pulse frequency clock (PFMCLK) drives pulse generation circuitry • Adjust to optimize frequency output range to your needs • D/A converter clock (DACCLK) drives external serial DACs • Set to maximum frequency that DAC can use • A/D converter clock (ADCCLK) drives external serial ADCs • Set to maximum frequency that ADC can use • All 4 clock frequencies controlled by Gate1[i].HardwareClockCtrl • 12-bit variable, 3 bits per signal (divide 40 MHz by 2N, N = 0 to 7) • Each clock settable to 40 MHz, 20 MHz, 10 MHz, … , 312 kHz

  13. Digital Delay Anti-Noise Filter • Cascaded series of D (delay) flip-flops • Signal progresses thru once per SCLK cycle • Best 2-of-3 voting on outputs • Noise spike found in only one SCLK cycle is filtered out • Lower SCLK freq. filters wider spikes • Higher SCLK freq. permits higher count rates

  14. PMAC2 Servo IC Channel Encoder Circuitry • Digital incremental encoder interface for each channel • Programmable decoder • Signal format • Direction sense • Free running counter • High-frequency timers • Counter latched each phase cycle • Counter and timers latched each servo cycle • Counter latched on user-set trigger condition • Index and/or flag • Rising or falling edge • Latched counter and timer values read by processor

  15. PMAC2 Servo IC Incremental Sensor Decode • Multiple formats of incremental feedback accepted • Gate1[i].Chan[j].EncCtrl specifies how to decode signal = 0: Pulse-&-direction CW = 1: x1 quadrature CW = 2: x2 quadrature CW = 3: x4 quadrature CW = 4: Pulse-and-direction CCW = 5: x1 quadrature CCW = 6: x2 quadrature CCW = 7: x4 quadrature CCW = 8: Internal pulse-&-direction = 11: x6 3-phase Hall CW = 12: MLDT pulse timing = 15: x6 3-phase Hall CCW

  16. Timer-Based Position Extension • ASICs have timers counting at encoder sample clock (SCLK) rate • Measure time between last two counts • Measure time since last count • Ratio of two timer values is estimate of fractional count value • With PMAC2 ASIC, conversion table calculates ratio in software, combines with whole-count servo data • PMAC3 ASIC calculates fraction each SCLK cycle; can be used for phase, servo, trigger capture, compare

  17. ASIC Position Capture Functionality • Available in both PMAC2 and PMAC3 ASICs (enhanced in PMAC3) • Each encoder channel has own capture circuitry • Latches present encoder count value immediately on preset trigger condition • Checks for trigger every encoder sample clock (SCLK) cycle (in MHz) • Capture is exact to the count at any speed • Optionally can latch timer-based (1/T) sub-count extension value • Delay before software notices trigger does not affect accuracy of capture • Useful for homing, probing, registration • Power PMAC motor/axis “triggered moves” use capture automatically • Can use selected channel input flag in trigger • Can use encoder index pulse in trigger • Can use both flag and index in trigger • Can select levels of flag and index to cause trigger

  18. Capture Trigger Select • Gaten[i].Chan[j].CaptCtrl • Specifies trigger signals and levels • Consists of 4 control bits Bit 0 = 1: Use index in trigger Bit 1 = 1: Use flag in trigger Bit 2 = 1: Invert index Bit 3 = 1: Invert flag • Combination of index and flag gets precision from index, uniqueness from flag • Gaten[i].Chan[j].CaptFlagSel • Specifies which trigger flag used = 0: Use HOMEn flag = 1: Use MLIMn flag = 2: Use PLIMn flag = 3: Use USERn flag

  19. “Gating” the Index Pulse for Capture • Most encoder index pulses are one full line wide • Power PMAC ASICs can “gate” pulse to one quadrature state width before use in capture • Gating permits more repeatable capture count in either direction • Gating permits same count value to be captured in both directions • Gaten[i].Chan[j].GatedIndexSel = 0: Use ungated index = 1: Use index gated to 1 quad state • Gaten[i].Chan[j].IndexGateState = 0: Use high/high quad state = 1: Use low/low quad state

  20. ASIC Position Compare Functionality • Available in both PMAC2 and PMAC3 ASICs (enhanced in PMAC3) • Each channel has own compare circuitry • Toggles “EQU” output state in hardware when encoder count reaches preset value • Comparison made every encoder sample clock (SCLK) cycle (in MHz) • No need for software intervention after initial setup • For precise triggering of outputs (e.g. lasers) and measurements • Can compare to own channel’s count, or first channel’s count, as set by saved setup element Gaten[i].Chan[j].Equ1Ena • Chan[0] output is logical OR of all compare circuits using this counter • Can set both sides of output pulse (“A” and “B”) • Can set “auto-increment” distance for repeated pulse interval • Supports pulse output frequencies of several MHz • No high-frequency software routine required for uniform pulse train

  21. PMAC2 Servo IC Position Compare Elements • Two non-saved 24-bit compare-position elements • Gate1[i].Chan[j].CompA • Gate1[i].Chan[j].CompB • Units of whole counts, referenced to power-on/reset position • Both toggle channel compare output when encoder counter value passes • Non-saved 24-bit auto-increment element, units of whole counts • Gate1[i].Chan[j].CompAdd • Value added to/subtracted from CompB when CompA reached • Value added to/subtracted from CompA when CompB reached • Initial values of CompA and CompB must “bracket” starting position • Minimum (non-zero) effective increment of 4 counts • 2-bit non-saved initial compare output forcing element • Gate1[i].Chan[j].EquWrite • Bit 1 (value 2) is state to be forced • Bit 0 (value 1) = 1 causes this state to be forced (auto-cleared to 0)

  22. Compare Auto-Increment Functionality • Supports repeated, evenly spaced pulses • Software sets 3 registers to start • CompA • CompB • CompAdd • Software can force initial output state • After this, hardware operates without further software intervention

  23. Position Compare Output Patterns • If CompAdd = 0, auto-increment is disabled, and each pulse must be set up in software • If CompAdd > 0, ASIC automatically increments CompA and CompB in direction of motion when other position is reached; permits set of evenly spaced pulses with just initial setup • With EquWrite, can force initial state; can set up for high-true or low-true pulses

  24. PMAC2 Servo IC Channel Output Circuitry • 3 phases per channel (A, B, C), each with 1 command register • Each phase has 2 output circuits • A & B phases have PWM (digital comparator) and DAC (shift register) • C phase has PWM and PFM (hardware adder/accumulator with overflow pulse output) • Gate1[i].Chan[j].OutputMode specifies which signals are output from IC Bit 0 = 0: A/B phases output PWM Bit 0 = 1: A/B phases output DAC Bit 1 = 0: C phase output PWM Bit 1 = 1: C phase output PFM • Correct setting depends on what hardware is used with IC

  25. PMAC3 ASIC Write-Protect Mechanism • Most saved setup elements in DSPGATE3 are “write protected” • Cannot change the values of these elements unless IC register for Gate3[i].WpKey contains the proper value ($AAAAAAAA) • Procedure for writing to write-protected element: • Write value of $AAAAAAAA to Gate3[i].WpKey • Write new desired value to write-protected element • ASIC automatically clears value of Gate3[i].WpKey • Power PMAC Script environment automatically copies value of software element Sys.WpKey to Gate3[i].WpKey before writing to protected element • User simply writes key value once to Sys.WpKey to permit changes • Value of Sys.WpKey is not saved, so must be written in after each power-up/reset to permit changes • IDE element setup controls automatically set key value for you • In C environment, must use an explicit write to Gate3[i].WpKey before each write to protected element

  26. PMAC3 ASIC Clock Generation • Gate3[i].PhaseServoDir specifies output (= 0) or input (= 3) of clocks • Gate3[i].PhaseFreq sets internal phase clock frequency (in Hertz) • Gate3[i].ServoClockDiv sets division of servo clock from phase clock • Gate3[i].Chan[j].PwmFreqMult derives channel fPWM from fPhase (0.5x – 3.5x) • Gate3[i].PhaseClockDiv sets division of external phase clock for internal use • Gate3[i].PhaseClockMult sets multiplication of internal phase clock for external use

  27. PMAC3 IC Hardware Clock Signals • These control specific hardware functions of IC • Each signal frequency independently controllable by setup element • Each element has 4-bit range (divide 100 MHz by 2N, N = 0 to 15) • Each clock settable to 100 MHz, 50 MHz, 25 MHz, … 3 kHz • Encoder sample clock (SCLK) by Gate3[i].EncClockDiv • Pulse frequency clock (PFMCLK) by Gate3[i].PfmClockDiv • D/A converter clock (DACCLK) by Gate3[i].DacClockDiv • A/D [encoder] clock (ADCENCCLK) by Gate3[i].AdcEncClockDiv • A/D [amplifier] clock (ADCAMPCLK) by Gate3[i].AdcAmpClockDiv • Flag filter clock (FILCLK) by Gate3[i].FiltClockDiv • For “de-glitching” input flags, error-detection (e.g. encoder loss) circuits • Divided down from SCLK, not 100 MHz

  28. PMAC3 ASIC Channel Incremental Encoder Circuitry

  29. PMAC3 ASIC Incremental Sensor Decode • Multiple formats of incremental feedback accepted • Gate3[i].Chan[j].EncCtrl specifies how to decode signal = 0: Pulse-&-direction CW = 1: x1 quadrature CW = 2: x2 quadrature CW = 3: x4 quadrature CW = 4: Pulse-and-direction CCW = 5: x1 quadrature CCW = 6: x2 quadrature CCW = 7: x4 quadrature CCW = 8: Internal pulse-&-direction CW = 9: Pulse-up/pulse-down CW = 11: x6 3-phase Hall CW = 12: Internal pulse-&-direction CCW = 13: Pulse-up/pulse-down CCW = 15: x6 3-phase Hall CCW

  30. PMAC3 ASIC Channel Timers • Each servo channel has high-frequency timers with multiple uses • Gate3[i].Chan[j].TimerMode specifies which use is made = 0: “Hardware 1/T” position extension (default) • Each SCLK cycle, divides time since last count by time between last two counts to get fractional count estimation • On phase clock, servo clock, and trigger, this fractional value is latched into low 10 bits of position register • When fractional value passes CompA or CompB value (and whole-count value matches), channel compare state is toggled = 1: MLDT pulse echo timing • Starts counting at 600 MHz on output pulse • Latches timer on receipt of echo pulse from MLDT = 2: Trigger input timing • Measures time from start of servo cycle to capture trigger event = 3: PFM pulse counter • For simulated position feedback from PFM output to stepper drive • Permits use of channel’s encoder counter for real (“confirmation”) encoder

  31. Standard Sine Encoder Interpolation Principle

  32. Auto-Correcting Sine Encoder Interpolation Principle

  33. PMAC3 ASIC Sine Encoder Setup • External to ASIC, sine and cosine signals from encoder feed: • Comparators to create digital quadrature into channel decoder and counter • ADCs to create numerical values into AdcEnc[0] and AdcEnc[1] • Gate3[i].Chan[j].EncCtrl set to 3 or 7 for “x4” quadrature decode • Gate3[i].Chan[j].AdcOffset[0] and [1] set to compensate for analog biases; automatically added to input values • Each phase and servo clock cycle: • On rising clock edge (after Gate3[i].EncLatchDelay ADC clock cycles), encoder counter is latched and ADCs are strobed • Data is clocked in from serial ADCs • Arctangent of corrected ADC values is computed • If Gate3[i].Chan[j].AtanEna = 1, on falling clock edge arctangent value is placed into low 14 bits of servo and phase position registers, below whole-line value latched from counter • Arctangent value cannot be used for asynchronous trigger capture; but timer-based estimation can be

  34. Resolver Principle of Operation • Controller outputs sinusoidal output signal of fixed magnitude and frequency • This AC signal on rotor couples by transformer effect to the two feedback signals on stator, offset by 90° from each other • Strength of coupling to each feedback signal is dependent on rotor angle • Rotor angle can be computed from relative magnitudes of the feedback signals

  35. PMAC3 ASIC Resolver Setup • Gate3[i].ResolverCtrl specifies sinusoidal excitation parameters • 32-bit value represented by 8 hex digits • Bits 31 – 24 (digits 1 & 2) specify phase shift of output • Values of 0 – 255 represent 0 – 50% of cycle shift • Set experimentally to maximize Gate3[i].Chan[j].SumOfSquares magnitude* • Bits 23 – 22 (part of digit 3) specify magnitude of output • Values of 0 – 3 represent 25%, 50%, 75%, 100% of maximum • Set experimentally to maximize feedback magnitude without saturation* • Bits 21 – 20 (part of digit 3) specify frequency of output • Values of 0 – 3 represent fphase, fphase/2, fphase/4, fphase/6 • Set for frequency closest to manufacturer’s recommendation • Sine and cosine feedback signals read thru ADCs into Gate3[i].Chan[j].AdcEnc[0] and [1] each phase cycle • Gate3[i].Chan[j].AdcOffset[0] and [1] set to compensate for analog biases; automatically added to input values • ASIC automatically computes arctangent from corrected inputs; 16-bit result found in Gate3[i].Chan[j].Atan * IDE setup window automates this process

  36. PMAC3 ASIC Serial Encoder Setup • Gate3[i].SerialEncCtrl specifies serial encoder setup information for all IC channels • 32-bit value represented as 8 hex digits • Bits 31 – 20 (digits 1 – 3) specify serial clocking frequency • Bits 17 – 16 (part of digit 4) specify trigger clock (phase or servo) and edge • Bits 15 – 08 (digits 5 & 6) specify delay from edge to encoder strobe • Bits 07 – 00 (digits 7 & 8) specify serial protocol: SPI, SSI, EnDat, Hiperface, Sigma I/II/III/V, Tamagawa, Panasonic, Mitutoyo, Kawasaki • Gate3[i].Chan[j].SerialEncCmd specifies command info for channel • 32-bit value represented as 8 hex digits • Continuous or one-shot triggering • Protocol-specific info such as parity, # of bits, Gray/binary, output command • Gate3[i].Chan[j].SerialEncDataA contains (low) 32 bits of position data • Gate3[i].Chan[j].SerialEncDataB contains high position bits, status, error information

  37. Serial Encoder Interface Timing

  38. PMAC3 ASIC Trigger Capture Setup Elements • Same as PMAC2 Servo IC, but adds capability to select flags from another servo channel • Gate3[i].Chan[j].CaptCtrl // Capture trigger edge specification Bit 0 = 1: Use index in trigger Bit 1 = 1: Use flag in trigger Bit 2 = 1: Invert index Bit 3 = 1: Invert flag • Gate3[i].Chan[j].CaptFlagSel // Capture flag type used = 0: Use HOME flag = 1: Use MLIM flag = 2: Use PLIM flag = 3: Use USER flag • Gate3[i].Chan[j].CaptFlagChan // Channel for capture flag used = 0: Flag from IC’s 1st channel = 1: Flag from IC’s 2nd channel = 2: Flag from IC’s 3rd channel = 3: Flag from IC’s 4th channel • Gate3[i].Chan[j].GatedIndexSel // Capture w/ “ungated” or “gated” index = 0: Use ungated index = 1: Use index gated to 1 quad state wide • Gate3[i].Chan[j].IndexGateState // Select “gating” quadrature state = 0: Use high/high quad state = 1: Use low/low quad state

  39. PMAC3 ASIC Servo Output Channel • 4 phases per channel (A, B, C, D), each with 1 command register • Each phase has 2 output circuits • A, B, & C phases have PWM (digital comparator) and DAC (shift register) • D phase has PWM and PFM (hardware adder/accumulator with overflow pulse output) • Gate3[i].Chan[j].OutputMode specifies which signals are output from IC Bit k = 0: Phase k outputs PWM Bit k = 1: Phase k outputs DAC, PFM • Possible to “pack” A & C, B & D command values (16 bits each) into 32-bit register with Gate3[i].Chan[j].PackOutData = 1

  40. PMAC3 ASIC Position Compare Elements • Saved 1-bit setup element selects encoder counter used for compare • Gate3[i].Chan[j].Equ1Ena = 0: Use Chan[j] counter = 1: Use Chan[0] counter • Two non-saved 32-bit compare-position elements • Gate3[i].Chan[j].CompA • Gate3[i].Chan[j].CompB • 20 bits of integer count, 12 bits of fraction (units of 1/4096 count) • Referenced to power-on/reset position • Both toggle channel compare state when encoder counter value passes • Fractional component compared to “hardware 1/T” count fraction • Non-saved 32-bit auto-increment element • Gate3[i].Chan[j].CompAdd • 20 bits of integer count, 12 bits of fraction (units of 1/4096 count) • Value added to/subtracted from CompB when CompA reached • Value added to/subtracted from CompA when CompB reached • Can be less than one count in size

  41. PMAC3 ASIC Position Compare Elements (cont.) • Non-saved 2-bit initial compare output forcing element • Gate3[i].Chan[j].EquWrite • Bit 1 (value 2) is state to be forced • Bit 0 (value 1) = 1 causes this state to be forced (auto-cleared to 0) • Act of forcing state disables first auto-increment (so initial CompA and CompB states do not have to “bracket” starting position) • Channel compare output-formation saved setup elements • Each channel’s output formed as logical combination of internal compare states • Gate3[i].Chan[j].EquOutMask: 4-bit element specifying which channels’ internal compare states are ORed into this channel’s compare output • Bit k = 1: Use Chan[k] internal compare state ORed into Chan[j] compare output • Default uses only the same channel’s internal compare state • Gate3[i].Chan[j].EquOutPol = 0 does not invert combined value for output (default) = 1 inverts combined value for output

  42. PMAC3 ASIC Position Compare Circuitry

  43. PMAC3 IC Windowing of Compare Outputs

  44. PMAC3 IC Capture/Compare Interrupt • Capture and compare events can interrupt CPU at highest priority • Custom ISR can react quickly to prepare for next event • Typically store captured position to RAM buffer • Typically load next compare position from RAM buffer • Updates to 75 kHz • Keep ISR short!

  45. IOGATE Data Structure Elements • GateIo[i].DataReg[j] (j = 0 to 5) 8-bit hardware registers • GateIo[i].DataReg[j].k (k = 0 to 7) Specifies individual bit in register • In normal use, contain input or output state of signal(s) • Can also specify setup configuration of matching signal(s) • GateIo[i].CtrlReg 8-bit setup register • Bits 6 & 7 specify use of data registers = 0: Use for input/output data > 0: Use for setup data • Bits 0 – 5 specify direction of matching data register I/O • Hardware setup values cannot be saved • Multiplexing means saving operation would not be robust in operation • GateIo[i].Init. saved software elements contain setup values automatically written to hardware registers on power-up/reset • On re-initialization, Power PMAC configures these software registers based on most common use of auto-detected I/O cards • User can change these values

More Related