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EE 241 Sp’09 FINAL Project Presentation. Design of a Low Power Content Addressable Memory (CAM). Scott Beamer Mehmet Akgul. Why do we need CAMs?. Current applications: Networking hardware, i.e. routers Cache T ag Lookup (CPUs) Design bottlenecks High energy consumption Large area
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EE 241 Sp’09 FINAL Project Presentation Design of a Low Power Content Addressable Memory (CAM) Scott Beamer Mehmet Akgul
Why do we need CAMs? • Current applications: • Networking hardware, i.e. routers • Cache Tag Lookup (CPUs) • Design bottlenecks • High energy consumption • Large area • Desired future applications: • Reverse tagged directory for multi-core architectures Our Study: Use EDP as a metric to compare major CAM design methods, demonstrate the pros and cons of individual techniques, and combine them in the optimum way to achieve a low power, high speed CAM design.
CAM Cell Operation MISMATCH Precharge Match Line MATCH LINE MATCH 1 0 Set Search Line 1 0 0 1 SEARCH LINE SEARCH LINE Evaluate
CAM Cell – NAND Version Precharge Match Line Discharge Path MATCH MISMATCH 1 0 Set Search Line 1 0 1 0 0 1 Evaluate
CAM Power Consumption Charged full swing every cycle Wasteful in power MATCH LINE SRAM SEARCH LINES Complementary SL → Activity factor = 1 Area, Delay and Energy Penalty
NOR Cell Analysis N k SL Energy ML Energy
NAND Cell Analysis Discharge Path M M M X M M Does not discharge – no energy lost Expected number of NAND cells that switch and consume power
NAND-NOR Hybrid Design N-k k NOR Matchlines charge only if all preceding NAND match NAND section discharge when all cells match Find k to optimize EDP k Etot & Dtot
Precomputation of 1’s Count All previous methods focused on ML – What about search line power? 0 1 0 1 # of 1 DATA Search pattern 0 1 1 0 0 0 0 1 1 0 1 1 ML Activated 1 0 CAM 1’s CAM 1 0 1 0 0 0 MATCH Impossible Cases 1 1 Search Pattern Saves half the search lines Less loading on match lines 1’s Count Reduced Power – Delay– Area
Optimized Hybrid Design What is the optimum combination of all these methods? NAND Cells 1’s Count NOR Cells Energy α 1/2k Half # of SL Fast Slow Overhead High power NAND 1’s Cnt NAND 1’s Cnt NOR NOR NAND NOR 1’s Cnt Slow Sub-optimal design Slow Low Power Fast MediumPower (C) (B) (A)
Conclusion • NAND Cell can achieve very low energy consumption at high delay cost • NOR Cell can achieve high speed, but consumes high power • To minimize EDP, one should use the optimum number of NAND cells in front of the low swing NOR chain. • To maintain ML-SL energy balance, use precombination as a method to reduce the number of search lines by half, and further reducing the activity of ML by 50%. • The optimum combination of these individual techniques can be achieved by using NANDs and precoding in front, which conditionally activates the following NOR matchlines, resulting in optimized energy-delay tradeoffs.