Low Power Memory

1. Low Power Memory

2. Agenda • What constitutes low power memory • Variations & vendors of low power memory • How to interface using CoolRunner-II

3. What is Low Power Memory • Devices feature additional power saving options: • Advanced self refresh modes • Deep power down mode • Low voltage power supply (1.8V, 2.5V, 3.3V) • Low standby current • Automatic power down • Advanced architecture and memory cell structure • Advanced packaging options

4. Advanced Architecture • Improved cell structure • UtRAM: uni-transistor memory cell structure • Prefetch architecture creates high speed devices

5. TCSR • Temperature Compensated Self Refresh • Ambient temperature adjusts refresh rate • Capacitor loses charge quicker at high temperature • Decrease refresh rate at lower temperatures • Minimized standby current during standby • Selectable for: 15°C, 45°C, 70°C, 85°C • Requires an external temperature sensor

6. PASR • Partial Array Self Refresh • Specify which banks are enabled

7. DPD • Deep Power Down • Maximum power reduction • Memory data is not retained • Acts as “soft switch-off”

8. Available Devices • Infineon MobileRAM (synchronous lower power DRAM) • Cypress MoBL (mobile static RAM) • Samsung • UtRAM • Low power SRAM • Mobile SDRAM • Micron • Mobile SDRAM • Cellular RAM

9. Mobile SDRAM Features • Fully synchronous • Internal pipeline architecture • Programmable burst length (1, 2, 4, 8, page) • TCSR • PASR power saving self-refresh • DPD • Up to 70% power savings over standard SDRAM devices in self-refresh mode

10. Mobile SDRAM Commands • NOP (Deselect SDRAM device) • ACTIVE (Opens row in specified bank for access) • READ (Select bank and column, and start READ burst) • WRITE (Select bank and column, and start WRITE burst) • DEEP POWER DOWN (Maximum power savings, data is not retained) • PRECHARGE (Deactivates open row in specified bank or all banks) • AUTO REFRESH or SELF REFRESH (Retains data in SDRAM) • LOAD MODE REGISTER (Defines operating mode of SDRAM)

11. Timing Specifications • For example, tRCD = 20 ns, with 125 MHz clock = 3 clock cycles • Parameter tRCD = delay controller must wait between ACTIVE and a READ/WRITE command

12. Read Command

13. Write Command

14. Deep Power Down Mode Upon exit DPD mode: NOP for 200 us Precharge all banks Issue 8 Auto Refresh commands Initialize Mode Register & Extended Mode Register

15. Why CoolRunner-II • Low standby current < 100 uA • Easy system integration with memory devices • Perfect target device for portable and handheld applications Mobile SDRAM System Bus

16. CPLD Design

17. State Machine Components • CAS latency 2-bit counter • Write burst 4-bit counter • Read burst 4-bit counter (implements burst up to 8) • Mode Register • CAS, burst length

18. State Machine

19. Conclusion • Complete downloadable VHDL reference design: XAPP394 • CoolRunner-II is the perfect target device for interfacing to low power memory devices • CoolRunner-II allows seamless system integration • CoolRunner-II is the ideal low power memory controller