Adaptive On-Chip Test Strategies for Complex Systems

1. Adaptive On-Chip Test Strategies for Complex Systems V. Stopjaková Department of Microelectronics, STU Bratislava, Slovakia

2. Electronics Industry Trends • Achieved successful penetration in different domains • Emergence of technology • Greater complexity • Increased performance • Higher density • Lowerpower dissipation

3. Market-Driven Products • Meet user Quality requirements • satisfying users to buy products • Created an unprecedented Dependency • market-driven products • Maintain competitive by providing: • Greater Product Functionality • Lower Cost • Reduced Interval(time to market) • Higher Reliability

4. ANALOG DRAM LOGIC DRAM LOGIC RF Analog FLASH FPGA Logic SRAM High Complexity: Mixed Systems • A single chip: Logic, Analog, DRAM blocks • Embed advanced blocks: • FPGA, Flash, RF/Microwave • Others • MEMS • Optical elements

5. High Complexity: Mixed Systems • How to test the mixed chip? • With external test only - need multiple ATE for a single chip: Logic ATE, Memory ATE, Analog ATE(Double/Triple Insertion) • Need special ATE with combined capabilities

6. Memory External Test Super ATE Pattern Generation Precision Timing Diagnostics Power Management Test Control Very high pin count Deep memory Slow serial SCAN Logic Mixed-Signal I/Os & Interconnects High Complexity: External Test • External Test Data Volume can be extremely high (function of chip complexity) • Requires deep tester memory for scan I/O pins • Slow test with long scan chains Source: LogicVision

7. External Test Standard Digital Tester Limited Speed/ Accuracy High Complexity: On-chip Test • Solution: Dedicated Built-In Test for embedded blocks • Tasks repartitioned into embedded test and external test functions On-chip Test Pattern Generation Result Compression Precision Timing Diagnostics Power Management Test Control Support for Board-level Test System-Level Test Memory Logic Mixed-Signal I/Os & Interconnects Chip, Board or System Source: LogicVision

8. Technology motivation • many CMOS defects escaping logic testing • physical imperfections causing delay faults • unmodeled faults (weak-1, weak-0) Quality & Reliability of IC affected ! • Conventional test methods not effective New on-chip test methods have to be applied

9. V DD defect I DD PMOS in out NMOS Supply Current Testing I DDT I DD I DDQ faulty PASS/FAIL reference fault-free t Figure 1 Principle of the supply current testing

10. IDDQ/T testing - realization • Off-chip measurement by external equipment • On-chip monitoring using Built-In Current (BIC) monitors • Off-chip monitors: • + no additional chip area needed • - slow measurement (decoupling capacitor) • - small current masked by noise • BIC Monitors: • sensitive, very fast and accurate • applicable in on-chip methods • chip area overhead • CUT perturbation

11. IDDQ testing crucial issues • Pass/Fail limit setting • represents fault-free value of IDDQcurrent • depends on number of factors: technology, type of circuits,... • if too high - defective circuits pass • if too low - undesired yield decrease (false fault detections) • Test vectors • Measurement Hardware

12. On-chip IDDQ Monitoring Principle V DD DUT I G ’ DD ND - Pass/Fail + Sensing element BICM Vref G ND Figure 2 On-chip supply current testing

13. Main requirements for on-chip current monitors • ability to sense high currents • testing of low-voltage circuits • a minimal number of extra pins • design simplicity • applicable for recent VLSI circuits Monitor development focused on: • effect on performance of the CUT • area overhead • testing speed • accuracy and sensitivity

14. Example of a quiescenton-chip monitor • based on CCII+ current conveyor • IDD current measurement  current comparison  IDDQ sampling Figure 3 Current conveyor based quiescent BIC monitor

15. BIC monitor layout • size of 1 bypass switch is 650m x 210m(80%) • total area of 0.22 mm2 Figure 4The core of the monitor layout

16. Evaluation results • resolution of 10nA • Pass/Fail limit of 50nA (sensitivity) • 1 MHz testing speed • VDD degradation max.100mV • area overhead of 0.22 mm2 • ability to handle large CMOS IC

17. Useful for Differential Analog Test Figure 5Experimental BIC monitor usage in a new ABIST approach

18. V DD R V DD ’ MET I I I DD MP1 MP2 MP1 MP2 I MIR CUT MN1 MN2 PB NB Current mirror IDD principle Figure 6 Current mirror principle of IDD monitoring

19. A Example of a transienton-chip monitor V DD V BIC monitor ref V DD’ D V mon Current CUT Mirror I I DD MIR C M S V offset Test Figure 7 Transient BIC monitor

20. Experimental digital chip • both BIC monitors integrated in BIC-MU • BIC-MU implemented into a digital circuit • a digital multiplier used as a CUT • fabricated in 0.7m CMOS • multiplier size 850m  850m • area of BIC-MU is 0.24mm2 • around 24% of the total chip area

21. Figure 8 Layout of the experimental chip

22. Versatility Problem of IDD Testing • IDD testing proven very successful for digital circuits • Dedicated fault class only • Use in submicron technologies limited • IDD testing for analog IC not straightforward • Large variety of analog IC • Specifications and behavior unique • Difficult to generalize analog tests • Validation up to now done using functional criteria Current consumption analysis using Neural Networks

23. Artificial Neural Networks Approach • Current signature analysis for presence of abnormal (faulty) behavior • Massively parallel and distributed structures capable of adaptation • No explicit Pass/Fail limit formulation required • Excellent versatility • Accuracy and sensitivity • Reduced number of TP (time to test)

24. IDD 1, 0 time or freq 0, 1 (BAD) (GOOD) IDD analysis using ANN Figure 9ANN-based analysis of IDD

25. bk wk1 x1 yk uk (uk) xP wkP Mathematical model Figure 10 Mathematical model of an artificial neuron

26. Activation function Figure 11 Activation function with top and bottom decision levels

27. ANN Classification of tested ICs • ANN with two outputs: n1, n2 • Classification within top/bottom decision levels n1  TDL & n2  BDL  PASS n1  BDL & n2  TDL  FAIL Otherwise  Non Classified

28. Analog DUT Example • Two-stage CMOS operational amplifier • A pulse used as input stimuli • Good patterns: technology parameters and temperature variations • Faulty behavior: basic defects injected (GOS, DOP, SOP, DSS, GSS, GDS)

29. Effect of the GOS Fault Figure 12 Effect of the GOS faults on IDD signal in time and frequency domain

30. Effect of the DSS Fault Figure 13 Effect of the DSS fault on IDD signal in different domains

31. ANN setup • 660 tested power supply current waveforms • 200 faulty patterns • 460 fault-free patterns • 32 input nodes • various training set: 200, 100, 76, 50 and 26 • various number of hidden units: 2, 6, 10, 14, 18, 22 • top decision level: 0.9 • bottom decision level: 0.1 • 10 independent measurements

32. Classification results Figure 14 Percent Correct Classification (PCC) for time domain

33. Classification results(2) Figure 15 Percent Correct Classification for frequency domain

34. Conclusions • To ensure quality of SoC Technologies: • On-chip Test is added into the designs of embedded cores • New adaptive on-chip approaches needed for different test functions • On-chip current monitoring effective but not versatile and limited to CMOS digital circuit • ANN classification of defective IC • ability of testing mixed-signal circuits • ability of sensing negligible differences • possibility to analyse other circuit’s parameters

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