Strategies for Post-Silicon Debug of Complex Integrated Circuits and Systems-on-Chip

1. 1 Strategies for Post-Silicon Debug of Complex Integrated Circuits and Systems-on-Chip Brad Quinton, Dept. of Electrical and Computer Engineering, University of British Columbia Vancouver, BC

2. 2 IBM Cell, ADM’s Opteron and Fusion, Intel’s Atom and Core 2 Duo… In fact I am working with a company right now architecting a 65nm SoC, and when you run the numbers you are compelled to integrate… IBM Cell, ADM’s Opteron and Fusion, Intel’s Atom and Core 2 Duo… In fact I am working with a company right now architecting a 65nm SoC, and when you run the numbers you are compelled to integrate…

3. 3 Bugs, bugs, everywhere...! IBM Cell, ADM’s Opteron and Fusion, Intel’s Atom and Core 2 Duo… In fact I am working with a company right now architecting a 65nm SoC, and when you run the numbers you are compelled to integrate… IBM Cell, ADM’s Opteron and Fusion, Intel’s Atom and Core 2 Duo… In fact I am working with a company right now architecting a 65nm SoC, and when you run the numbers you are compelled to integrate…

4. 4 The Culprit: Design Complexity IBM Cell, ADM’s Opteron and Fusion, Intel’s Atom and Core 2 Duo… In fact I am working with a company right now architecting a 65nm SoC, and when you run the numbers you are compelled to integrate… IBM Cell, ADM’s Opteron and Fusion, Intel’s Atom and Core 2 Duo… In fact I am working with a company right now architecting a 65nm SoC, and when you run the numbers you are compelled to integrate…

5. 5 The Effect: Costs and Risks ? IBM Cell, ADM’s Opteron and Fusion, Intel’s Atom and Core 2 Duo… In fact I am working with a company right now architecting a 65nm SoC, and when you run the numbers you are compelled to integrate… IBM Cell, ADM’s Opteron and Fusion, Intel’s Atom and Core 2 Duo… In fact I am working with a company right now architecting a 65nm SoC, and when you run the numbers you are compelled to integrate…

6. 6 Outline

7. 7 IC Development this increasing complexity is creating many challenges for both verification and validation.this increasing complexity is creating many challenges for both verification and validation.

8. 8 IC Development this increasing complexity is creating many challenges for both verification and validation.this increasing complexity is creating many challenges for both verification and validation.

9. 9 IC Development this increasing complexity is creating many challenges for both verification and validation.this increasing complexity is creating many challenges for both verification and validation.

10. 10 IC Development this increasing complexity is creating many challenges for both verification and validation.this increasing complexity is creating many challenges for both verification and validation.

11. 11 Validation: A High Stakes Game

12. The Need for Post-Silicon Debug

13. 13 “The device won’t boot. Now what?!” Where is the problem: software, hardware, board level….Where is the problem: software, hardware, board level….

14. 14 Visibility is Key

15. Existing Solutions

16. 16 Existing Solutions

17. 17 Existing Solutions

18. 18 On-chip Emulation Trace buffers on internal system busses are a simple example of On-chip EmulationTrace buffers on internal system busses are a simple example of On-chip Emulation

19. 19 Emerging Implementations

20. Our Proposal

21. 21 Our Proposal

22. 22 Reconfigurable DFD analogous to the widespread use of Design for Test (DFT) methodologies, new Design for Debug (DFD) concepts are emerging embedded reconfigurable => small amount of FPGA logicanalogous to the widespread use of Design for Test (DFT) methodologies, new Design for Debug (DFD) concepts are emerging embedded reconfigurable => small amount of FPGA logic

23. 23 Reconfigurable DFD analogous to the widespread use of Design for Test (DFT) methodologies, new Design for Debug (DFD) concepts are emerging embedded reconfigurable => small amount of FPGA logicanalogous to the widespread use of Design for Test (DFT) methodologies, new Design for Debug (DFD) concepts are emerging embedded reconfigurable => small amount of FPGA logic

24. 24 Framework

25. 25 High-level Architecture

26. 26 High-level Architecture Memory or trace buffer is also integrated in the PLC.Memory or trace buffer is also integrated in the PLC.

27. 27 High-level Architecture

28. 28 High-level Architecture Consider a bug that we encountered on the out first generation product at Teradici. The audio processor had FIFO lock-up problem, but only for one specific (an very rare) packet size. If software knows, it can quickly re-intialize the FIFO, and operation will continue.Consider a bug that we encountered on the out first generation product at Teradici. The audio processor had FIFO lock-up problem, but only for one specific (an very rare) packet size. If software knows, it can quickly re-intialize the FIFO, and operation will continue.

29. 29 Our Proposal - Key Advantages

30. 30 Key Challenges

31. Results

32. 32 Network Topology We have developed a unique network topology that leverages the programmability of the PLC to reduce network costs: complete debug node selection flexibility 50% of the area and 50% of the depth previous topologies hierarchical construction appropriate for ICs Details: B.R. Quinton and Steven J.E. Wilton, “Concentrator Access Networks for Programmable Logic Cores on SoCs”, IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 2005. B.R. Quinton, S.J.E. Wilton, “Post-Silicon Debug Using Programmable Logic Cores”, Proceedings of the IEEE International Conference on Field-Programmable Technology, Singapore, pp. 241-247, December 2005.

33. 33 Network Implementation We have developed and evaluated two network implementations: synchronous and asynchronous, each achieves high throughput: synchronous networks up to 830 MHz in 90nm technology asynchronous networks up to 910 MHz in 90nm technology reasonable area costs Details: B.R. Quinton, M.R. Greenstreet, S.J.E. Wilton, “Practical Asynchronous Interconnect Network Design”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 5, pp. 579-588, May 2008.

34. 34 Programmable Logic Interface We have developed new programmable structures that are integrated into a regular programmable logic fabric to significantly increase the throughput of interface circuits: system bus interfaces up to 254 MHz in 180nm regular synchronous interfaces up to 694 MHz in 180nm very small area increase in the PLC ( less than 0.4%) limited impact on the PLC interconnect Details: B.R. Quinton, S.J.E. Wilton, "Embedded Programmable Logic Core Enhancements for System Bus Interfaces", Proceedings of the International Conference on Field-Programmable Logic and Applications, Amsterdam, pp. 202-209, August 2007. B.R. Quinton and Steven J.E. Wilton, “Programmable Logic Core Enhancements for High Speed On-Chip Interfaces”, accepted for publication in IEEE Transactions on VLSI, 2009.

35. 35 Area Overhead To understand the area overhead of our scheme for a range of ICs we created a set of parameterized models We used a 90nm standard cell process We targeted the 90nm IBM/Xilinx PLC with a capacity of approximately 10,000 ASIC gates The network was implemented using standard cells All area numbers are post-synthesis, but pre-layout

36. 36 Area Overhead

37. 37 Area Overhead

38. 38 Design for Debug Going Forward

39. 39 How do we select the correct debug nodes? How do we judge the quality of our debug infrastructure before it is used? What is the “coverage” metric? How do we integrate hardware DFD with software debug? How do we integrate DFD with DFT? What is the overlap? Can this reduce costs? Can we use software algorithms to infer the value of nodes that have not been directly observed?

40. End.