April 30, 2014

1. Automated Generation of Functional Verification for MPSoC April 30, 2014 Marcela Šimková Head of Verification and Testing, Codasip Ltd.

2. Motivation • MPSoC (Multi-Processor Systems on Chip): • Functional verification is time-demanding: • implementation of verification environments, • preparation of different test scenarios, • preparation of reference models, • long verification runs. • Demand for verification tools, which are: • Increase in design complexity = increase in verification complexity SOFTWARE AWARE TIME-EFFECTIVE AUTOMATED

3. MPSoCDesign • Processors(general purpose, ASIPs, combination) + peripherals: • IP cores, • in-house development. • MPSoCdescription languages: • Hardware Description Languages (HDL), like VHDL, Verilog, • Architecture Description Languages (ADL), like CodAL, nML.

4. MPSoCVerification • Different verification approaches: functional, formal, ABV, CDV, verification IPs, emulation, etc. • Incremental verification: • TREND: system-level verification (hardware + software).

5. ProposedSolution MPSoC Design • Support of several frontends for HDL, ADL, etc. • Library of available processors. • Intermediate representation in IP-XACT standard: • complex architecture description, • interconnections, • extendibility. MPSoC Verification • Automated generation of UVM verification environments: • flexible (processors with SW, peripherals) • complete (UVM basic components, scoreboarding structures, coverage monitors) • Automated generation of reference models.

6. Extraction • For automatedgeneration of UVM environments, we need to extract information about: • interconnection of components, • direction of interface signals (driver vs. monitor), • stimulation of input interface signals. • Two approaches:

7. UVM Generation Challenges • Generating reference models. • From high-level ADL description (top-down approach). • Instruction-set simulators for processors, simulation models for components. • DPI connection to reference model for all components of MPSoC or a sub-set of them. • Setting coverage targets, assertions. • Basic set of coverage targets and assertions is pre-generated. • Support of functional, assertions, and code coverage. • High-level verification management. • 1:1 or 1:N mapping of software applications to processors.

8. UVM Generation

9. UVM Generation • Sobel edge detection MPSoCdesigned in Codasip Framework [1]. • 16-bit low-power cache-less Codix-STREAM [2] processors.

10. Demonstration Example - GUI

11. Generated UVM Environment

12. Verification OK GM Output Picture Input Picture DUT Output Picture

13. Inserted Bug

14. Verification Failure GM Output Picture Input Picture DUT Output Picture

15. Configuration of Controllers

16. Bug Detection in Simulator

17. Conclusion • Automatedgeneration of MPSoC functional verification environments. • Two approaches for extraction of information: • analysis of ADL components, • analysis of RTL/Netlist components. • Generating reference models, coverage scenarios and assertions. • High-level verification management (SW aware MPSoC verification).