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LHCb Outer Tracker Upgrade AMC40 firmware. Outline OT architecture Front end box architecture Actel TDC Data GBT interface Data format Test Setup AMC40/TP test setup. Outer Tracker. One of the 432 Front Ends with 128 straw channels each. LV,HV distr. Front-end box architecture.
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LHCb Outer Tracker UpgradeAMC40 firmware • Outline • OT architecture • Front end box architecture • Actel TDC • Data GBT interface • Data format • Test Setup • AMC40/TP test setup Antonio Pellegrino, Tom Sluijk, WilcoVink,
Outer Tracker • One of the 432 Front Ends with 128 straw channels each LV,HV distr Antonio Pellegrino, Tom Sluijk, Wilco Vink
Front-end box architecture 20 february 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,
OT Front-end boxes • 432 Front end boxes, each: • 1 master GBT / power board (replaces: GOL board) • TFC distribution • 1 Master GBT (hardwired configured, except clocks) • 1 SCA for monitoring (power, temperature, etc.) • 4 Actel TDC boards (replaces: OTIS boards) • 2 data transmitter GBT’s • 1 SCA (Actel TDC conf. GBT conf., monitoring) • 8 ASDBLR boards (unchanged) • Total: • 3888 GBT’s • 432 TFC Master GBT’s (Bidir) • 3456 Data GBT’s • 2160 SCA’s Tom Sluijk, Wilco Vink, Antonio Pellegrino
Front-end box • 1 GBT master/power board (replaces: GOL board) • Versatile link transceiver, <-> Master GBT • TFC signals • 1 SCA for monitoring (power, temperature, etc.) • 8 Optical data transmitters • 4 dual transmitters versatile link OR • 12-way optical transmitter, based on KK Ghan’svcsel driver (8+4 spare) • Power supplies based on CERN SM01C DC/DC conv. • 4 Actel TDC boards (replaces: OTIS boards) • 2 data transmitter GBT’s • Wide bus format data transmitters • One used for clocks, BxClkTpClk, TFC,clk • Spare clocks for TDC • 1 SCA • Actel re-programming via JTAG • GBT configuration • 4 Threshold DAC • Temperature monitoring • Soft reset Actel • 1 Actel Pro-asic A3PE1500 • 32 channel, 5-bits TDC • Zero suppression • 8 ASDBLR boards (unchanged) 20 february 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,
Actel TDC • Pro-Asic A3PE1500 (4 FPGA’s/FE-box) • 32 channel 5 bits TDC • Based on 4 320 MHz clocks(2 edges and 90phase shifted) • fixed placement (3 variants: top, right, bottom) • Zero suppression • Two wide-bus 28bits@160MHz GBT outputs 20 february 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,
Data GBT interface • Two options uses identical PCB, different Actel firmware • 8 Data GBT’s per FE-box • One ZS output bus per 16 channels • No bandwidth limitations • NZS full bandwidth readout capable • 4 data GBT’s per FE-box • One ZS output bus per 32 channels • Bandwidth limit, lower cost, lower luminosity • Wide-bus GBT format 28b@160MHz 20 february 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,
Two 16 ch. TDC in one FPGA Dual GBT’s 16 channel TDC Zero-supp 16 stages Fifo Readout GBT1 16 channel TDC Zero-supp 16 stages Fifo Readout GBT2 Actel FPGA Data Format (9 channels hit): GBT1 27 0 16 bits Hit pattern channel (0-15) 4 bits BX cnt 8 bits Status Padded ‘0’ 5 bits Data 5 bits Data 5 bits Data 5 bits Data 5 bits Data Max 4 words when all channels are hit GBT2 16 bits Hit pattern channel (16-31) 4 bits BX cnt 8 bits Status Padded ‘0’ 5 bits Data 5 bits Data 5 bits Data 5 bits Data Max 4 words when all channels are hit 20 february 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,
32 channel TDC with single GBT 32 channel TDC Zero-supp 32 stages Fifo Readout GBT Actel FPGA Data Format (9 channels hit): GBT 27 0 16 bits Hit pattern channel (0-15) 4 bits BX cnt 8 bits Status Data 5 bits Data 5 bits Data 16 bits Hit pattern channel(16-31) 5 bits Data 5 bits Data 5 bits Data 5 bits Data 5 bits Data 5 bits Padded ‘0’ s 5 bits Dat Max 8 words when all channels are hit 20 february 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,
OTTOv2 Test Setup • StratixIV 230 evaluation board • Dummy GBT, based on code Sophie Baron • Not yet implemented • Small TFC • Data buffer (512MB DDR3) • I2C over Ethernet, dummy ECS/SCA • Interfaces through 2 Wide bus buses with OTTOv2 • OTTDC to Optical: OTTOv2 • Prototype board with combined TDC board (OTIS) and Master GBT board (GOL) • Actel 32 channel TDC • Snap 12 optical receiver/transmitter • Versatile link: • Dual transmitter (data GBT) • Bi-directional (master GBT) • SM01C radiation hard DC/DC power converters • SCA Mezzanine (SCA pin-out not known) • Threshold DAC 20 february 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,
Test setup 20 february 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,
Test Setup Altera Dummy GBT slave Altera Dummy GBT master 1GbEth 1GbEth Snap12 Rx Snap12 Tx SCA Actel TDC Vers.Link Power ASDBLR left ASDBLR right 20 february 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,
AMC40/TP test setup overview 20 february 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,
Mini-DAQ with AMC40/TP • OTTOv2 with master/slave StratixIV • Data GBT emulated • Master GBT (not implemented) • TFC signals • ECS via E-Link to SCA • Code available ?? • Test setup as 1/4 Front end box • Needs GBT wide-bus FPGA code • AMC40/TP used for mini-DAQ and TFC/ECS • Needs AMC40/TP firmware • TFC/ECS • DAQ 20 february 2013 Antonio Pellegrino, Tom Sluijk, WilcoVink,
AMC40/TP mini-DAQ • Firmware “requirements” for first tests with OTTOv2 proto setup, First thoughts: • Dual data GBT input “data grabber” • Receives two GBT’s wide-bus data streams • Packet builder, MEP based on two links ??? • Scalable, start with small MEP builder ??? • DAQ->data-storage • Sends data through “standard” output to test DAQ (= 10GbE host PC) • TFC/ECS • Control of master GBT(dummy in StratixIV) • Is this done before? • Used as an TFC master • TFC (PVSS <-> CCPC <-> GBT <-> SCA <-> OTTO) • PC control software available? , start with command line CCPC ?? • Slow control ECS • ECS (PVSS <-> CCPC <-> GBT <-> SCA <-> OTTO) • PC control software available? , start with command line CCPC ?? Antonio Pellegrino, Tom Sluijk, Wilco Vink
