1 / 8

MICE Tracker Firmware Development

MICE Tracker Firmware Development. Firmware tasks AFPGA/DFPGA protocol and trigger buffering AFPGA/DFPGA bidirectional data bus VLSB firmware Schedule/Fallback Position. Terry Hart, NFMCC Friday Meeting, May 4, 2007. AFPGA/DFPGA Firmware. VLSB memory banks storing charge and time data.

jackson-daugherty
Download Presentation

MICE Tracker Firmware Development

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. MICE Tracker Firmware Development • Firmware tasks • AFPGA/DFPGA protocol and trigger buffering • AFPGA/DFPGA bidirectional data bus • VLSB firmware • Schedule/Fallback Position Terry Hart, NFMCC Friday Meeting, May 4, 2007

  2. AFPGA/DFPGA Firmware VLSB memory banks storing charge and time data • Protocol for bidirectional data flow developed. • Bidirectional data flow tested on board and shown to work at 53.104 MHz • AFPGA/DFPGA communication interface done • Work ongoing in buffering triggers in AFPGA. DFPGA directs DFPGA and AFPGA data flow bitmaps from TriP-t chips bitmaps directing zero-suppression charge and time data AFPGA controls ADC and TriP-t operation Done Terry Hart, NFMCC Friday Meeting, May 4, 2007

  3. VLSB Firmware VLSB memory banks storing charge and time data • VLSB = VME LVDS Serdes Buffer • Tracker data storage modules • Used for KEK test beam • Used by D0 for diagnostics • Modifications for MICE • Fast clear of VLSB memory • Overwrite memory addresses when there’s null data so that data are stored in continuous memory blocks. • Enable DMA block transfers DFPGA directs DFPGA and AFPGA data flow AFPGA controls ADC and TriP-t operation Done Terry Hart, NFMCC Friday Meeting, May 4, 2007

  4. VLSB Progress • VLSB Memory Fast Clear • Should be possible with simple state machine in VLSB firmware. • Should be finished next week • Memory Address Modification • Initial ideas for firmware modifications formulated • DMA Block Transfer • Working on compiling existing firmware • Test stand set up to diagnose problems with existing spreadsheet which has block transfer settings Terry Hart, NFMCC Friday Meeting, May 4, 2007

  5. Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec TriP-t/ADC Control Firmware Hardware tests DFPGA/AFPGA I/O Bus Board test at 53.104 MHz Board test at 55 MHz Simulations at different frequencies Data transfer protocol AFPGA Firmware Write firmware controlling bitmap transfers Test pipeline/buffer operation Test mode development DFPGA Firmware Make 4-level trigger buffer Data format Event aggregation VLSB Firmware Data block transfer Fast clear of memory banks Suppress writing zeros to memory Done Done Done Terry Hart, NFMCC Friday Meeting, May 4, 2007

  6. Fallback Position • DAQ goal: Keep up with 600 kHz trigger rate. • At start of MICE in Aug./Sept., original firmware is sufficient for initial low data rate. • With TriP-t zero-suppression, tracker can keep up with almost 300 kHz now. • June is target time to have firmware capable of keeping pace with 600 kHz trigger rate roughed out and in advanced testing stages. Terry Hart, NFMCC Friday Meeting, May 4, 2007

  7. 600 480 360 240 120 0 1000 2000 3000 4000 4-level Buffering 3-level Buffering 2-level Buffering 1-level Buffering No Buffering Where we are. Recordable Muon Rate (kHz) Digitization Time (ns)

  8. MICE Tracker Firmware Summary • AFPGA control of TriP-t and ADCs done and tested • AFPGA and DFPGA firmware development and testing underway. • VLSB modifications specified and work is underway • Task list, schedules and fallback positions developed Terry Hart, NFMCC Friday Meeting, May 4, 2007

More Related