ISSUES IN TIMING

1. ISSUES IN TIMING

2. The Clock Skew Problem Clock Rates as High as 1 GHz in CMOS! f t t t f f f ’ ’’ ’’’ In Out CL1 CL2 CL3 R1 R2 R3 t i t t l,min r,min t t l,max r,max Clock Edge Timing Depends upon Position

3. Delay of Clock Wire Clock line capacitance For DEC Alpha is 3.75nF!!

4. Constraints on Skew

5. Clock Constraints in Edge-Triggered Logic

6. Positive and Negative Skew

7. Clock Skew in Master-Slave Two Phase Design

8. T f f1 1 T T T f12 f21 f2 f 2 clock d f ’ overlap 1 d - T f12 clock period T Clock Skew in 2-phase design new data applied to CL 2 previous data latched into M 2 t > - T d f min 12 t < T + d - T f12 max

9. How to counter Clock Skew?

10. Clock Distribution

11. Clock Network with Distributed Buffering

12. Example: DEC Alpha 21164

14. Clock Skew in Alpha Processor

15. Self-timed and asynchronous design

16. Self-timed pipelined datapath

17. Completion Signal Generation

18. Completion Signal Generation

19. Completion Signal in DCVSL

20. Self-timed Adder

21. Hand-shaking Protocol

22. Event Logic — The Muller C-element

23. 2-phase Handshake Protocol

24. Example: Self-timed FIFO

25. 4-phase Handshake Protocol (or RTZ)

26. 4-phase Handshake Protocol -Implementation Data Sender Receiver logic logic Data Accepted Data Ready Req S C C Ack Handshake logic

27. Asynchronous-Synchronous Interface

28. A Simple Synchronizer

29. Synchronizer: Output Trajectories

30. Simulated Trajectory versus One Pole Model

31. Mean Time to Failure

32. Example

33. Cascaded Synchronizers Reduce MTF

34. Arbiters

35. Synchronization at System Level

36. Skew of Local Clocks vs Reference

37. Phase-Locked Loop Based Clock Generator

38. Ring Oscillator

39. Example of PLL-generated clock