1 / 37

Evolution of Implementation Technologies

Evolution of Implementation Technologies. Discrete devices: relays, transistors (1940s-50s) Discrete logic gates (1950s-60s) Integrated circuits (1960s-70s) e.g. TTL packages: Data Book for 100’s of different parts Map your circuit to the Data Book parts Gate Arrays (IBM 1970s)

fayre
Download Presentation

Evolution of Implementation Technologies

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Evolution of Implementation Technologies • Discrete devices: relays, transistors (1940s-50s) • Discrete logic gates (1950s-60s) • Integrated circuits (1960s-70s) • e.g. TTL packages: Data Book for 100’s of different parts • Map your circuit to the Data Book parts • Gate Arrays (IBM 1970s) • “Custom” integrated circuit chips • Design using a library (like TTL) • Transistors are already on the chip • Place and route software puts the chip together automatically • + Large circuits on a chip • + Automatic design tools (no tedious custom layout) • - Only good if you want 1000’s of parts trend toward higher levels of integration Xilinx FPGAs - 1

  2. Gate Array Technology (IBM - 1970s) • Simple logic gates • Use transistors toimplement combinationaland sequential logic • Interconnect • Wires to connect inputs andoutputs to logic blocks • I/O blocks • Special blocks at peripheryfor external connections • Add wires to make connections • Done when chip is fabbed • “mask-programmable” • Construct any circuit Xilinx FPGAs - 2

  3. Programmable Logic • Disadvantages of the Data Book method • Constrained to parts in the Data Book • Parts are necessarily small and standard • Need to stock many different parts • Programmable logic • Use a single chip (or a small number of chips) • Program it for the circuit you want • No reason for the circuit to be small Xilinx FPGAs - 3

  4. Programmable Logic Technologies • Fuse and anti-fuse • Fuse makes or breaks link between two wires • Typical connections are 50-300 ohm • One-time programmable (testing before programming?) • Very high density • EPROM and EEPROM • High power consumption • Typical connections are 2K-4K ohm • Fairly high density • RAM-based • Memory bit controls a switch that connects/disconnects two wires • Typical connections are .5K-1K ohm • Can be programmed and re-programmed in the circuit • Low density Xilinx FPGAs - 4

  5. Programmable Logic • Program a connection • Connect two wires • Set a bit to 0 or 1 • Regular structures for two-level logic (1960s-70s) • All rely on two-level logic minimization • PROM connections - permanent • EPROM connections - erase with UV light • EEPROM connections - erase electrically • PROMs • Program connections in the _____________ plane • PLAs • Program the connections in the ____________ plane • PALs • Program the connections in the ____________ plane Xilinx FPGAs - 5

  6. Making Large Programmable Logic Circuits • Alternative 1 : “CPLD” • Put a lot of PLDS on a chip • Add wires between them whose connections can be programmed • Use fuse/EEPROM technology • Alternative 2: “FPGA” • Emulate gate array technology • Hence Field Programmable Gate Array • You need: • A way to implement logic gates • A way to connect them together Xilinx FPGAs - 6

  7. Field-Programmable Gate Arrays • PALs, PLAs = 10 - 100 Gate Equivalents • Field Programmable Gate Arrays = FPGAs • Altera MAX Family • Actel Programmable Gate Array • Xilinx Logical Cell Array • 100 - 1000(s) of Gate Equivalents! Xilinx FPGAs - 7

  8. Field-Programmable Gate Arrays • Logic blocks • To implement combinationaland sequential logic • Interconnect • Wires to connect inputs andoutputs to logic blocks • I/O blocks • Special logic blocks at periphery of device forexternal connections • Key questions: • How to make logic blocks programmable? • How to connect the wires? • After the chip has been fabbed Xilinx FPGAs - 8

  9. Tradeoffs in FPGAs • Logic block - how are functions implemented: fixed functions (manipulate inputs) or programmable? • Support complex functions, need fewer blocks, but they are bigger so less of them on chip • Support simple functions, need more blocks, but they are smaller so more of them on chip • Interconnect • How are logic blocks arranged? • How many wires will be needed between them? • Are wires evenly distributed across chip? • Programmability slows wires down – are some wires specialized to long distances? • How many inputs/outputs must be routed to/from each logic block? • What utilization are we willing to accept? 50%? 20%? 90%? Xilinx FPGAs - 9

  10. Altera EPLD (Erasable Programmable Logic Devices) • Historical Perspective • PALs: same technology as programmed once bipolar PROM • EPLDs: CMOS erasable programmable ROM (EPROM) erased by UV light • Altera building block = MACROCELL 8 Product Term AND-OR Array + Programmable MUX's I/O Pin Seq. Logic Block Xilinx FPGAs - 10 Programmable polarity Programmable feedback

  11. Altera EPLD Altera EPLDs contain 8 to 48 independently programmed macrocells Personalized by EPROM bits: Flipflop controlled by global clock signal local signal computes output enable Flipflop controlled by locally generated clock signal + Seq Logic: could be D, T positive or negative edge triggered + product term to implement clear function Xilinx FPGAs - 11

  12. Altera Multiple Array Matrix (MAX) AND-OR structures are relatively limited Cannot share signals/product terms among macrocells Logic Array Blocks (similar to macrocells) Global Routing: Programmable Interconnect Array EPM5128: 8 Fixed Inputs 52 I/O Pins 8 LABs 16 Macrocells/LAB 32 Expanders/LAB Xilinx FPGAs - 12

  13. LAB Architecture Expander Terms shared among all macrocells within the LAB Xilinx FPGAs - 13

  14. P22V10 PAL Supports large number of product terms per output Latches and muxes associated with output pins Xilinx FPGAs - 14

  15. Actel Programmable Gate Arrays Rows of programmable logic building blocks + rows of interconnect Anti-fuse Technology: Program Once Use Anti-fuses to build up long wiring runs from short segments 8 input, single output combinational logic blocks FFs constructed from discrete cross coupled gates Xilinx FPGAs - 15

  16. Actel Logic Module Basic Module is a Modified 4:1 Multiplexer Example: Implementation of S-R Latch Xilinx FPGAs - 16

  17. Actel Interconnect Interconnection Fabric Xilinx FPGAs - 17

  18. Actel Routing Example Jogs cross an anti-fuse minimize the # of jobs for speed critical circuits 2 - 3 hops for most interconnections Xilinx FPGAs - 18

  19. Xilinx Programmable Gate Arrays • CLB - Configurable Logic Block • 5-input, 1 output function • or 2 4-input, 1 output functions • optional register on outputs • Built-in fast carry logic • Can be used as memory • Three types of routing • direct • general-purpose • long lines of various lengths • RAM-programmable • can be reconfigured Xilinx FPGAs - 19

  20. Programmable Interconnect I/O Blocks (IOBs) Configurable Logic Blocks (CLBs)

  21. The Xilinx 4000 CLB Xilinx FPGAs - 21

  22. Two 4-input functions, registered output Xilinx FPGAs - 22

  23. 5-input function, combinational output Xilinx FPGAs - 23

  24. CLB Used as RAM Xilinx FPGAs - 24

  25. Fast Carry Logic Xilinx FPGAs - 25

  26. Xilinx 4000 Interconnect Xilinx FPGAs - 26

  27. Switch Matrix Xilinx FPGAs - 27

  28. Xilinx 4000 Interconnect Details Xilinx FPGAs - 28

  29. Global Signals - Clock, Reset, Control Xilinx FPGAs - 29

  30. Xilinx 4000 IOB Xilinx FPGAs - 30

  31. Xilinx FPGA Combinational Logic Examples • Key: General functions are limited to 5 inputs • (4 even better - 1/2 CLB) • No limitation on function complexity • Example • 2-bit comparator: A B = C D and A B > C D implemented with 1 CLB(GT) F = A C' + A B D' + B C' D' (EQ) G = A'B'C'D'+ A'B C'D + A B'C D'+ A B C D • Can implement some functions of > 5 input Xilinx FPGAs - 31

  32. Xilinx FPGA Combinational Logic • Examples • N-input majority function: 1 whenever n/2 or more inputs are 1 • N-input parity functions: 5 input/1 CLB; 2 levels yield 25 inputs! 5-input Majority Circuit 9 Input Parity Logic CLB CLB 7-input Majority Circuit CLB CLB CLB CLB Xilinx FPGAs - 32

  33. Xilinx FPGA Adder Example • Example • 2-bit binary adder - inputs: A1, A0, B1, B0, CIN outputs: S0, S1, Cout Full Adder, 4 CLB delays to final carry out 2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out Xilinx FPGAs - 33

  34. Computer-Aided Design • Can't design FPGAs by hand • Way too much logic to manage, hard to make changes • Hardware description languages • Specify functionality of logic at a high level • Validation: high-level simulation to catch specification errors • Verify pin-outs and connections to other system components • Low-level to verify mapping and check performance • Logic synthesis • Process of compiling HDL program into logic gates and flip-flops • Technology mapping • Map the logic onto elements available in the implementation technology (LUTs for Xilinx FPGAs) Xilinx FPGAs - 34

  35. CAD Tool Path (cont’d) • Placement and routing • Assign logic blocks to functions • Make wiring connections • Timing analysis - verify paths • Determine delays as routed • Look at critical paths and ways to improve • Partitioning and constraining • If design does not fit or is unroutable as placed split into multiple chips • If design it too slow prioritize critical paths, fix placement of cells, etc. • Few tools to help with these tasks exist today • Generate programming files - bits to be loaded into chip for configuration Xilinx FPGAs - 35

  36. Xilinx CAD Tools • Verilog (or VHDL) use to specify logic at a high-level • Combine with schematics, library components • Synopsys • Compiles Verilog to logic • Maps logic to the FPGA cells • Optimizes logic • Xilinx APR - automatic place and route (simulated annealing) • Provides controllability through constraints • Handles global signals • Xilinx Xdelay - measure delay properties of mapping and aid in iteration • Xilinx XACT - design editor to view final mapping results Xilinx FPGAs - 36

  37. Applications of FPGAs • Implementation of random logic • Easier changes at system-level (one device is modified) • Can eliminate need for full-custom chips • Prototyping • Ensemble of gate arrays used to emulate a circuit to be manufactured • Get more/better/faster debugging done than with simulation • Reconfigurable hardware • One hardware block used to implement more than one function • Functions must be mutually-exclusive in time • Can greatly reduce cost while enhancing flexibility • RAM-based only option • Special-purpose computation engines • Hardware dedicated to solving one problem (or class of problems) • Accelerators attached to general-purpose computers Xilinx FPGAs - 37

More Related