Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

SpezielleAnwendungen des VLSI – EntwurfsApplied VLSI design Course and contest Results of Phase 3 Sebastian Kruse

Optimizations • Change of coefficent • Now no adder is needed for calculation • Look for higher metric at lower voltage area • Comparison between different adder types

Carry Skip Adder • Delay time of O() • Variable block size • Area compared to RCA: CLA CLA CLA CLA CLA CLA 0 1 0 1 0 1

Han Carlson / Brent Kung • Han Carlson • Brent Kung Source: Binary Adder Architectures for Cell-BasedVLSI andtheirSynthesis, Prof.Dr. W. Fichtner, 1997

Comparison between FPGA and ASIC • FPGA { Frequency / Area} • Carry Skip: 324.044 MHz / 143 LUT • Ripple Carry: 426,439 MHz / 109 LUT • Han Carlson: 332,779 MHz / 128 LUT • Brent Kung: 293,083 MHz / 135 LUT • ASIC { Frequency / Pdyn/ Pleak } • Carry Skip: 356 MHz / 3,156 nW / 19,330 nW • Ripple Carry:390 MHz / 3,135 nW / 19,185 nW • Han Carlson: 356 MHz / 3,146 nW / 19,241 nW • Brent Kung: 356 MHz / 3,148 nW / 19,244 nW

Filter response • FPGA ASIC

Results • Used parameters for synthesis in Synopsys: • set frequency 0.001 • compile_ultra • set_max_leakage_power 0 mw • set_max_dynamic_power 0 mw • set_wire_load_mode top

Future improvements • Change type of adder (phase 3) • Brent Kung adder • Han Carlson adder • Carry skip adder • Only do an addition for important digits • Summation compression (Wallace tree) • Carry save representation

Thank you for your attention!

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design