Anna Macchiolo L. Andricek, M. Beimforde, H.G. Moser, R. Nisius, R.H. Richter, P. Weigell

1. SLID interconnection technology and TSVs for the upgrade of the ATLAS pixel system Anna Macchiolo L. Andricek, M. Beimforde, H.G. Moser, R. Nisius, R.H. Richter, P. Weigell Max-Planck-Institut für Physik & MPI Halbleiterlabor (HLL) Munich In collaboration with AIDA kick-off meeting, WP3 session, CERN 16.02.2011

2. SLID interconnection and TSVs for a new module concept

3. Thin planar pixel sensors

4. Sensor thinning technology at MPP-HLL • For the n-in-p wafers the process completed up to step #4. The handle wafer will be used as a support also during the ASIC interconnection phase. • Production characteristics: • 8 n-in-p 6“ wafers. • Different active thicknesses: 75μm and 150μm. • Complete electrical characterization of pixel devices before and after irradiation – CCE on strips

5. 150 mm Sensor thinning technology at MPP-HLL • For the n-in-p wafers the process completed up to step #4. The handle wafer will be used as a support also during the ASIC interconnection phase. CCE measurements after irradiations

6. MPP 3D R&D Program: demonstrator module • Step I: • ASIC thinned to 200 µm • thin sensors / ASIC interconnection using SLID • No TSV, integrated fan-out on sensor for service connection • Step II: • TSV etched in the read-out chip on the front-side on every wire bonding pad to route signal and services to the ASIC backside • ASIC thinned to 50 µm • thin sensors /ASIC interconnection using SLID

7. MPP 3D R&D Program: demonstrator module • Step I: • ASIC thinned to 200 µm • thin sensors / ASIC interconnection using SLID • No TSV, integrated fan-out on sensor for service connection • Step II: • TSV etched in the read-out chip on the front-side on every wire bonding pad to route signal and services to the ASIC backside • ASIC thinned to 50 µm • thin sensors /ASIC interconnection using SLID

8. MPP 3D R&D Program: demonstrator module • Step I: • ASIC thinned to 200 µm • thin sensors / ASIC interconnection using SLID • No TSV, integrated fan-out on sensor for service connection • Step II: • TSV etched in the read-out chip on the front-side on every wire bonding pad to route signal and services to the ASIC backside • ASIC thinned to 50 µm • thin sensors /ASIC interconnection using SLID

9. The SLID interconnection

10. EMFT SLID Process • Alternative to bump bonding (less process steps “lower cost” (EMFT)). • Small pitch possible (~ 20 mm, depending on pick & place precision). • Stacking possible (next bonding process does not affect previous bond). • Wafer to wafer and chip to wafer possible. • However: no rework possible.

11. Daisy chains: wafer-to-wafer SLID • SLID efficiencies measured with daisy chains structures (wafer to wafer connections): A. Macchiolo et al. “Application of a new interconnection technology for the ATLAS pixel upgrade at SLHC“ http://cdsweb.cern.ch/record/1234896/files/p216.pdf • “Chip to wafer” interconnection with the daisy chain structures resulted in a chip placement precision on the handle wafer not accurate enough (chips of different sizes, stemming from different wafers).

12. SLID interconnection of FE-I3 pixels (I) FE-I3 chips after electroplating of the SLID pads Sensor-ASIC interconnection is achieved with a “chip to wafer” approach: • 4 n-in-p 6” SOI sensor wafers with pixels sensors FE-I3 compatible have been left undiced. • Electroplating to create the SLID pads has been performed at the wafer level both on sensors and chips SLIDpads in the FE-I3 chip over the original openings in the passivation layer SLIDpads in the chip balcony to increase the mechanical stability • SLID pads of 27x60 mm2: determination of optimal SLID pad placement and size based on results of daisy chain production.

13. FE-I3 pixels SLID interconnection of FE-I3 pixels (II) SOI sensor wafer with the connected FE-I3 chips after release of the handle wafer • After electroplating, FE-I3 chips are singularized and reconfigured on a 6” handle wafer. This is removed after the interconnection to the sensor wafer. • First assembly, composed by FE-I3 chips interconnected with SLID to a 75 mm thick sensor wafer, has been finished last week. • Due to the misalignment (~20 mm) in the placement of a fraction of the chips on the handle wafer only 5-6 assemblies over the original 10, can be read-out . • The test of the FE-I3 modules will be carried out with the ATLAS USBpix read-out. SLID cross-section

14. Pull test with FE-I3 chips interconnected with SLID • Pull test performed on modules assembled with bad FE-I3 chips and dummy sensors. • 0.5 – 0.8 g per single SLID connection needed to disconnect the FE-I3 chip Weight needed for the disconnection of a single FE-I3 module

15. Through Silicon Vias

16. handling substrate Trough Silicon Vias processing handling substrate CMOS bulk Etching (Bosch process) on FE-I3 8” wafers. 60 µm deep TSVs with lateral dimensions of 3 x 10 µm2 Back thinning to expose the TSV, backside isolation Insulation, filling with tungsten Electroplating, metallization on the ASIC back side • Face to face connection for our project (also die up connections are possible). • 2.5 Ohm/per via (including SLID). • No significant impact on chip performance (test performed on MOS transistors). Electroplating, metallization on the ASIC front side

17. TSV in the FE-I3 chips • First etching trials • Performed in the un-thinned FE-I3 chips of one designated test-wafer • Etched to a depth of ~ 69 mm • Rough cut/break along the long direction of the test structure shows the structure of the vias and of the trench around them • Preparation of the hot FE-I3 wafer • Aluminum etching on the fan-out pads • Nitride etch • Local planarisation by depositing and etching of SACVD-Oxide • Next steps • Perform via etching and filling in the hot FE-I3 wafer • Connect the readout chip with SLID to the hot sensor wafers  measure the module with the USBPix system

18. Summary and Outlook • MPP is developing a new pixel module with: • Thin planar pixel sensors (75 mm and 150 mm thick) on SOI wafers • 3D integration with SLID and ICV (Fraunhofer EMFT) • Wafer-to-wafer SLID: high interconnection efficiency • FE-I3 chips were connected to a SOI sensor wafers with SLID. Soon to be measured with the ATLAS USBPix system • TSVs etched on test FE-I3 wafer. First photolithographic steps on the hot FE-I3 wafer.