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Verilog

Verilog. Matt Tsai. Verilog Application Introduction to Cadence Simulators Sample Design Lexical Conventions in Verilog Verilog Data Type and Logic System Structural Modeling Modeling Delay Using Compiler Controls Verilog Operators Behavioral Modeling Support for Verification

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Verilog

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  1. Verilog Matt Tsai

  2. Verilog Application • Introduction to Cadence Simulators • Sample Design • Lexical Conventions in Verilog • Verilog Data Type and Logic System • Structural Modeling • Modeling Delay • Using Compiler Controls • Verilog Operators • Behavioral Modeling • Support for Verification • Introduction to Using a Verilog Test Bench • Modeling Memories • High Level Constructs in Verilog • User Defined Primitives • Annotating SDF Timing

  3. IEEE 1364-1995, IEEE 1364-2001 • Behavioral: 無法看出電路特性 • RTL:可以看出電路特性 (logic synthesis) • Structural: bulit-in primitives,UDPs • RTL and structural 可混合描述 • Behavioral 和 RTL的區分要靠經驗 {RTL} always @(sl or a or b) if(!sl) out=a; else out=b; {Behavioral} for( ; ; ) for( ; ; ) . . .

  4. 3-9 • Compilation(1) Initialization(2) Simulation(3) • Verilog-XL simulator:Interpretive • 不會有暫存檔(1)(2)(3)一次完成 • NC Verilog simulator:compiled simulation • ncviog(1) ncelab(2) ncsim(3) • 當project很大時,只針對要修改部分重新compile即可 • VHDL and Verilog可以作整合 • Simulation algorithms • Time-based(SPICE) • Event-based(Verilog-XL and NC Verilog) • Cycle-based(依照clock,更大的time-based) 3-3

  5. run.f mux.v testbench.v 3-17 • verilog mux.v testbench.v • verilog –f run.f • The waveform display tool---signalscan • Read data from database • SHM database(非IEEE standard,only Cadence) • VCD(Value Change Dump) database(IEEE standard) 3-27 4-26 initial begin $shm_open(“lab.shm”); $shm_probe(“AS”); end initial begin $dumpfile(“lab.dump”); $dumpvars(); end

  6. module testbench //Data type declaration reg a,b,sel; wire out; //Instantiate modules MUX2_1 mux(out,a,b,sel); //Apply stimulus initial begin a=0;b=0;sel=0; #5 b=0; #5 b=1;sel=1; #5a=1; $finish; end //Display results initial $monitor($time,,”out=%b a=%b sel=%b”,out,a,b,sel); endmodule Template module testbench //Data type declaration //Instantiate modules //Apply stimulus //Display results endmodule • Testbench----behavioral • Procedural block • Initial • always 4-15

  7. Waveform database(SHM and VCD) $shm_open(“lab.shm”); $shm_probe(); $shm_close; $shm_save; $dumpfile(‘lab.dump”); $dumpvars(); $dumpflush; $dumpoff; $dumppon; $dumplinit(<file size>); $dumpall;

  8. Inside code Command line 8-3 • `include global.v • verilog mux.v global.v • timescale 1ns/100 ps • Lumped delay • nor n1(net1,a,b); • or #3 o1(out,c,net1); • Distributed delay • nor #2 n1(net1,a,b); • or #1 o1(out,c,net1); • Module path delay • Specify • (A=>O)=2; • (A=>O)=3; • (A=>O)=1; • //state dependent path delay • if(a) • (b=>x)=(5:6:7); • //state dependent delay 無else的語法 • Endspecify specify block 8-16

  9. Selecting simulation delay mode • Command line • +delay_mode_unit • +delay_mode_zero • +delay_mode_path • +delay_mode_distributed • Inside code • ‘delay_mode_unit • ‘delay_mode_zero • ‘delay_mode_path • ‘delay_mode_distributed Unit and zero delay modes: ignores all specify blocks, and reduces gate to unit or zero value. Distributed mode:ignores specify blocks, but leaves gate delays alone Path mode:ignores gate delays,but leaves specify blocks alone

  10. Parallel connection • (a,b => q,qb)=15; • (a=>q)=15; • (b=>qb)=15; • Full connection • (a,b *> q,qb)=15; • (a=>q)=15; • (b=>q)=15; • (a=>qb)=15; • (b=>qb)=15;

  11. 8-30 8-38,21-5 • Timing checks in Verilog(物理特性) • Setup,hold,pulse width,clock period,skew,recovery • SDF(Standard Delay Format) • tool-independent text format for representing timing data • Allows timing data to be shared between tools • Interconnect delay • 因製程技,使interconnection delay比gate delay大,下晶片需SDF File • IOPATH delay • A delay on legal path from an input port to an output port of a device

  12. Using Compiler Controls • Vendor-supplied verilog libraries • Simulating with verilog libraries • Encrypting your verilog source code • Additional simulator-specific topics

  13. Modeling component libraries 9-5 • To create verilog model libraries • Model each component(or cell) as separate module • Place related modules in either one file or one directory • You can model the functionality of each cell at two levels • Structural • UDPs,combinational logic and simple sequential logic • Behavioral • Procedural block • RAM,ROM

  14. 自建library `celldefine module full_adder(cout,sum,a_in,b_in,c_in); input a_in,b_in,c_in; output cout,sum; … … endmodule `endcelldefine … `celldefine module half_adder(cout,sum,a_in,b_in,c_in); input a_in,b_in,c_in; output cout,sum; … … endmodule `endcelldefine module full_adder(cout,sum,a_in,b_in,c_in); input a_in,b_in,c_in; output cout,sum; … … endmodule • verilog test.v –v lib.v • 若無-v會全部compile • 有-v用到才compile • 也可無`celldefine及-v,如一 • 般的file

  15. and2.v module and2(…) endmodule and3.v nor.v • verilog test.v –y ./mylib +libext+and2.v • 檔案名稱要和module名字相同 • 一個file內只能有一個module • 這些files全部都要放在library directory (Verilog model library directory)

  16. The `uselib compiler directive(only Cadence) 9-18 module adder(c_out,sum,a,b,c_in); Output c_out,sum; Input a,b,c_in; `uselib dir=/libs/FAST_LIB/ SN7486 u1(half_sum,a,b); Uselib dir=/libs/TTL/ libext=.v file=/libs/TTL/udp.lib SN7408 u2 (half_c,a,b); SN7486 u2 (sumc,c_in,half_sum); SN7432 u2 (c_out,tmp,half_c); SN7486 u1(half_sum,a,b); //ERROR endmodule

  17. Sizing and signing in Verilog 10-5 • 等號右邊一定是對的,指定到左邊時會自動truncate module sign_size; reg [3:0] a,b; reg [15:0] c; reg [3:0] regb,rega,num; initial begin a=-1; //1111 b=8;c=8; #10 b=b+a; //10111->0111 end initial #30 num=regb%rega; //num的正負號和regb相同 endmodule

  18. 10-21 • Equality operator • =:assignment operator • ==:the equality operator(數值比對) [1==1] • ===:the identity operator(型態上) [x===x] • val= rega= =regb; //rega=1,regb=1,val=1 • val= rega= =regc; //rega=1,regb=x,val=x • val= rega= =regc; //rega=z,regb=z,val=x • val= rega= = =regb; //rega=x,regb=x,val=1 • Conditional operator • assign out= sel= = 2’b00 ? a : • sel= = 2’b01 ? b : • sel= = 2’b10 ? c : d; 10-28

  19. Concatenation • new={regc[4:3],regd[7:5],regb[2]}; • Replication • new={ {4{regb}} , {2{regc}}}; • Procedural block • Behavioral modeling, not structural modeling • Two type:initial , always • It has the following component • Procedural assignment statements • High-level constructs(loops,conditional statements) • Timing controls • Procedural assignment • Inside procedural blocks • 等號左邊要reg才行

  20. Procedural timing control • # , @ , wait • 所有的procedural blocks同時執行 always wait(set) begin @(posedge clk) #3 q=1; #10 q=0; wait (!set); end 11-39 1.有可能會有race condition,但並非每次都會有race condition 2.race condition 是simulation 才會有,可以改變set信號再去 Simulation就可以了 3.實際電路不會,因本身就有delay了

  21. posedge clk 右邊算出 左右 • Inter-assignment • temp=b; • @(posedge clk) a=temp; • Intra-assignment • a = (posedge clk) b; 右邊算出,暫存在b’ posedge clk 左右 Data b c clk Interc Intrab

  22. Conditional statements • if-else • case • If-else階層超過2層時會有判斷優先權順序的路出現,故改用case • 若無else敘述,電路會變得很大 • Continuous assignment (assign) • Procedural block中不可用assign • wire out; • assign out=a&b; //explicit(建議使用) • wire inv=~in; //implicit

  23. To read the current simulation time • Verification system functions andtasks • $time (64-bits) • $stime (32-bits) • $realtime (real number) • $display • $strobe • $write • $monitor • Printing formatted time information • $timeformat(<unit>,<precision>,<suffix>,<min_width>) • $timeformat( -9 , 2, ”ns’ , 10 ); • $display(“%t”,$realtime); To support text output

  24. initial begin #10 date=20; $strobe($time,data); //30 $display($time,data); //20 data=30; end • $write vs.$display: $display會自動換行 • $strobe一定在event-query的最後面 14-20 File output initial begin integer MCD1; //每個檔只有一個bit為1,有一個bit保留,故最多可以開31個檔 MCD1=$fopen(“lab.dat”); $fdisplay(MCD1,”system reset at time %d”,$time); $fwrite(MCD1,”system reset at time %d”,$time); $fstrobe(MCD1,”system reset at time %d”,$time); $fmonitor(MCD1,”system reset at time %d”,$time); $fclose(MCD1) end

  25. 14-26 reg [0:7] mema[0:1023]; readmemb(“mem_file.txt,mema); • File input • $readmemb • $readmemh 00000000 01100001 00110010 11111100 11100010 0 mem_file.txt 0000_0000 0110_0001 0011_0010 //addresses 3-255 are not defined @100 //hex 1111_1100 @3FF 1110_0010 256 1023

  26. Design organization Vendor libraries Include files simulator compilation Design files simulation File input: Simulus, Expect patterns File output: Stimulus, result patterns

  27. Include files module clk_gen(clk); output clk; reg clk; `include “common.txt” …. endmodule //common.txt parameter initial_clock=1; parameter period=1; parameter max_cyc=1; parameter sim_end=period * max_cyc; … 1. parameter獨立在某一檔案中,並且詳細說明 2. 改變parameter,重新compile即是新的design

  28. Testbench給pattern的方式 • In line • Loop(behavioral),pattern要有規則 • array //loop initial begin for( ; ; ) @(negedge clk) stimulus=1; #20 $finish; end //in line initial fork data_bus=8’h00; addr=8’h3f; #10 data_bus=8’h45; #30 addr=8’h45; #60 $finish; join //array initial begin #20 stimulus=stim_array[0]; #20 stimulus=stim_array[1]; #20 stimulus=stim_array[2]; end

  29. 17-7 Verilog task and function • Task:input,output,inout,timing • Fuinction:input,return value,combinational,可建立自己的operator • Function 一定在等號右邊,不一定要在procedural blcok中 • Task:只能出現在procedural block中 module foo; input [7:0] loo; output [7:0] goo; wire [7:0] goo=test(loo); function [7:0] test input [7;0] bus; … test=return_test; endfunction endmodule always #5 clk=!clk; task ngg_clocks input [31;0] number_of_edges; repeat(number_of_edges) @(negedge clk); endtask initial begin … neg_clocks(3); end

  30. 不可synthesize • === • `uselib • initial • memory • / • Wait • String (5-17) • Named event (11-17)

  31. 所有的module不一定有 I / O Port • 名稱大小寫有差!!!!!但compiler會視為相同東西 • 宣告integer : Enter 旁的dot • 宣告compiler directive : ESC 下的dot • X unknown state is used for test • Net is unconditional update ,Register is conditional update • Define / Parameter difference (6-25) • L & H state (7-11)

  32. User Define Primitive • Verilog 可以加密!!!! (9-36) • 語法是 +autoprotected 或 `protect `endprotect • Zero delay loop (8-11) • Register array and memory addressing (6-30)

  33. Lab Cadence: /cadence/bin/icfb verilog signalscan Synopsys: source synopsys.cshrc da &

  34. #dollar setenv SYNOPSYS /usr/synopsys setenv LM_LICENSE_FILE 26585@lsfcu setenv SYNOPSYS_KEY_FILE $SYNOPSYS/admin/license/key set path=(/usr/bin/X11 $SYNOPSYS/sparcOS5/syn/bin $SYNOPSYS/iview2/bin $SYNOPSYS/sos/bin $path) source $SYNOPSYS/admin/install/sim/bin/environ.csh alias da design_analyzer # define COSSAP environment variables for the COSSAP user (csh version) # SYNOPSYS software is installed in /usr/synopsys # setenv COSSAP_DIR /usr/synopsys/sparcOS5/cossap # setenv COSSAP_KEYS /usr/synopsys/admin/license/key # network wide writable file holding the netlist number # setenv COSSAP_NEWSIM_SIM /usr/synopsys/sparcOS5/cossap/admin/install/newsim.sim # the default COSSAP project is derived from the login directory # if (! $?COSSAP_PROJECT) setenv COSSAP_PROJECT `basename ${HOME}` # define the COSSAP PATH # set path = ( ${COSSAP_DIR}/bin /opt/SUNWspro/bin $path ) # define a few directory switching commands for COSSAP # alias cdir 'cd ${HOME}/cossap/${COSSAP_PROJECT}/c' # alias ddir 'cd ${HOME}/cossap/${COSSAP_PROJECT}/d' # alias vdir 'cd ${HOME}/cossap/${COSSAP_PROJECT}/v' # alias tdir 'cd ${HOME}/cossap/costmp' # define COSSAP project switching command # alias scp 'set scp_project = \!:*; source ${COSSAP_DIR}/appl/utils/scp.csh' # set limit for file descriptors # limit descriptors 256 synopsys.cshrc

  35. .synopsys_dc.setup (design_analyzer的設定檔 ) 可更改designer及company欄位,其他不可更動,除非設計需要,如外加記憶體模組 … synopsys_dc.setup designer="Chin-Yi Tsai"; company="CIC" search_path={/app/cadtool/library/CIC_CBDK35_V3/Synopsys}+ search_path; link_library={cb35os142.db dw01.sldb,dw02.sldb,dw03.sldb,dw04.sldb,dw05.sldb}; target_library={cb35os142.db}; symbol_library={generic.sdb class.sdb}; synthetic_library={"standard.sldb"."dw01.sldb"."dw02.sldb"."dw03.sldb"."dw04.sldb"."dw05.sldb"}; vhdlout_use_packages={"IEEE.std_Logic_1164"."compass_lib.components"} vhdlout_write_top_configuration="true"

  36. /home/VLSILAB/ta/CB/ /home/VLSILAB/ta/CB/da/synopsys.cshrc

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