Verilog Basics

1. Verilog Basics Nattha Jindapetch November 2008

2. Agenda • Logic design review • Verilog HDL basics • LABs

3. Logic Design Review

4. Basic Logic gates

5. Additional Logic Gates

6. Two Types • Combinational circuit • No "memory" • Its output depends only upon the current state of its inputs. • Sequential circuit • Contains memory elements • Its output depends not only upon the current state of its inputs, but also on the current state of the circuit itself. • Two Styles: Synchronous and Asynchronous

7. Combinational Circuits: examples • Multiplexers • 2n x 1multiplexer receives 2ninputbits and n selectorbits, and outputs exactly one of the input bits, determined by the pattern of the selector bits.

8. Combinational Circuits: examples • Demultiplexers • 1 x 2n DMUX is the inverse of MUX • It takes 1 input and transmits that input on exactly one of its outputs, determined by the pattern of its n selector bits.

9. Combinational Circuits: examples • Encoders • 2n x nencoder takes 2n inputs and sets each of its n outputs, based upon the pattern of its inputs. • an encoder is the inverse of a decoder.

10. Combinational Circuits: examples • Decoders • An n x 2ndecoder takes n inputs and sets exactly one of its 2n outputs, based upon the pattern of its inputs.

11. Sequential Circuits • Circuits with feedback Cross-coupled NOR gates

12. Sequential Elements • Latches vs Flip-Flops • Latches work on Level-sensitive • Flip-Flops work on Edge-triggered • RS, JK, D, T

13. Counters • Synchronous counter • Clock of synchronous counter are same clock. • Asynchronous counter • Clock of second flip-flop is Q of first flip-flop. • The clock of asynchronous counter are different source.

14. Registers • A register is used for storing several bits of digital data. • It basically consists of a set of flip-flops. • each flip-flop representing one bit of the register. • Thus, an n-bit register has n flip-flops. A Simple Shift Register Consisting of D-type Flip-flops

15. Verilog HDL basics

16. HDL(Hardware Description Language) • Big picture: Two main HDLsout there • VHDL • Designedby committee on request of theDepartmentofDefense • Basedon Ada • Verilog HDL • Designedby a company for their own use • BasedonC • Bothnow have IEEE standards • Bothareinwideuse

17. Verilog Description Styles • Verilog supports a variety of description styles • Structural • explicitstructure of the circuit • e.g., each logic gate instantiated and connected to others • Behavioral • programdescribes input/output behavior of circuits • Mixed

18. Verilog Module module module-name (list-of-port); input/output declarations local net declarations parallel statements endmodule

19. co a b w0 w1 s w2 Structural Module: example1 module half_adder (s, a, b, co); input a, b; output s, co; wire w0, w1, w2; assign w0 = a & b, w1 = ~w0, w2 = a | b, s = w1 & w2, co = w0; endmodule

20. Structural Module: example1 module full_adder (s, a, b, co, ci); input a, b, ci; output s, co; wire w0, w1, w2; assignco = w1 | w2; half_adder i0 (.co(w1), .s(w0), .a(a), .b(b)); half_adder i1 (.co(w2), .s(s), .a(w0), .b(ci)); endmodule

21. Structural Module: example1 module adder4 (s, a, b, co, ci); input [3:0] a, b; input ci; output [3:0] s, output co; wire w0, w1, w2; full_adder i0 (.co(w0), .s(s[0]), .a(a[0]), .b(b[0]), .ci(ci)); full_adder i1 (.co(w1), .s(s[1]), .a(a[1]), .b(b[1]), .ci(w0)); full_adder i2 (.co(w2), .s(s[2]), .a(a[2]), .b(b[2]), .ci(w1)); full_adder i3 (.co(co), .s(s[3]), .a(a[3]), .b(b[3]), .ci(w2)); endmodule

22. Behavioral Module: example1 module adder4 (s, a, b, co, ci); input [3:0] a, b; input ci; output [3:0] s, output co; reg [3:0] s; reg co; always @(a or b or ci) {co, s} = a + b + ci; endmodule

23. Verilog Data Types • Possible Values: • 0: logic 0, false • 1: logic 1, true • X: unknown logic value • Z: High impedance state • Registers and Nets (wires) are the main data types • Integer, time, and real are used in behavioral modeling, and in simulation • Note that theyare not synthesized !

24. Verilog Registers • Abstract model of a data storage element • A reg holds its value from one assignment to the next • The value “sticks” • Register type declarations • reg a; // a scalar register • reg [3:0] b; // a 4-bit vector register

25. Verilog Nets • Nets (wires) model physical connections • They don’t hold their value • They must be driven by a “driver” (i.e. a gate output or a continuous assignment) • Their value is Z if not driven • Wire declarations • wire d; // a scalar wire • wire[3:0] e; // a 4-bit vector wire

26. Verilog Parameters • Used to define constants parameter size = 16, value = 8; wire [size-1:0] bus; // defines a 15:0 bus

27. Verilog Operators • Arithmetic operators: +, -, *, /, % • Logical operators: &&, ||, ! • Bitwise operators: &, |, ~, ^, ^~ • Equality operators: ==, !=, • Relational operators: >, <, >=, <= • Reduction operators: &, ~&, |, ~|, ^ • Shift operators: >>, << • Conditional: ?:

28. module mux4 (s, d, z); //bitwise operators input [1:0] s; input [3:0] d; output z; assign z =(~s[1] & ~s[0] & d[0]) | (~s[1] & s[0] & d[1]) | ( s[1] & ~s[0] & d[2]) | ( s[1] & s[0] & d[3]) ; endmodule Example2: 4:1 multiplexer

29. module mux4 (s, d, z); //using conditional operators input [1:0] s; input [3:0] d; output z; assign z = s[1] ? (s[0] ? d[3] : d[2]) : (s[0] ? d[1] : d[0]); endmodule Example2: 4:1 multiplexer

30. Verilog Assignments • Two types: • Continuous Assignments • assign values to nets • This means combinational logic • Procedural Assignments • assign values to registers • Only allowed inside procedural blocks (initial and always)

31. Continuous Assignments • Models combinational logic using a logical expression instead of gates • Assignment is evaluated whenever any signal changes wire a, b, out; assign out = ~(a & b); wire [15:0] sum, a, b; wire cin, cout; assign {cout,sum} = a + b + cin;

32. ProceduralAssignments • Assigns values to register types • They do not have a duration • The register holds the value until the next procedural assignment to that variable • They occur only within procedural blocks • initial and always • They are triggered when the flow of execution reaches them

33. always Blocks • When is an always block executed? • always • Starts at time 0 • always @(a or b or c) • Whenever there is a change on a, b, or c • Used to describe combinational logic • always @(posedge foo) • Whenever foo goes from low to high • Used to describe sequential logic • always @(negedge bar) • Whenever bar goes from high to low

34. Inside always blocks • Procedural assignments • if statements • case statements • for, while, forever statements • wait statements

35. Blocking vs Non-blocking

36. Blocking vs Non-blocking Blocking begin q1 = x1; q2 = q1; z1 = q2; end Non-Blocking begin q1 <= x1; q2 <= q1; z1 <= q2; end

37. Quick Review • Continuous assignments to wires • assign variable = exp; • Result in combinational logic • Procedural assignment to regs • Always inside procedural blocks (always blocks in particular for synthesis) • blocking • variable = exp; • non-blocking • variable <= exp; • Can result in combinational or sequential logic

38. Quick Review module name (args…); input …; // define inputs output …; // define outputs wire… ; // internal wires reg …; // internal regs, possibly output // the parts of the module body are // executed concurrently <continuous assignments> <always blocks> endmodule

39. comment inVerilog_HDL • // Single-line comment • /*…………. …………..*/ multiple-line comment module mux2_1(out,a,b,sel); // port declare. input a,b,sel; output out; wire sel_,a1,b1 /* structural design using logic operator mux2_1 */ not (sel_,sel); and (a1,a,sel),(b1,b,sel); or (out,a1,b1); endmodule;

40. Naming inVerilog_HDL • ข้อกำหนด ในการตั้งชื่อไฟล์ การตั้งชื่ออุปกรณ์ และการเชื่อมต่อ • สายสัญญาณ จะต้องไม่เป็นคำสงวนของภาษา • ระหว่างข้อความ หรือตัวเลข สามารถใช้ เครื่องหมาย _ หรือ $ ได้ • ตัวแรกที่ตั้งชื่อต้องเป็น ตัวอักษร a-z หรือ A-Z หรือ _ • ตัวอักษรตัวใหญ่ และ ตัวเล็ก จะมีความหมายแตกต่างกัน

41. ศึกษาเพิ่มเติม .... • Evita_Verilog • Teerayod_Verilog_Thai