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EE166 Project

EE166 Project. Frequency Dividers. Group Members. Hengky Chandrahalim Toai Nguyen Mike Tjuatja. Inputs and Outputs Features. Input -1 Clk_In at 5V <200MHz -1 RESET signal -4 VDDs at 5V -4 VSSs . Inputs and Outputs Features. Outputs -1 Output at 5V = Clk_In/2

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EE166 Project

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  1. EE166 Project Frequency Dividers

  2. Group Members • Hengky Chandrahalim • Toai Nguyen • Mike Tjuatja

  3. Inputs and Outputs Features • Input • -1 Clk_In at 5V <200MHz • -1 RESET signal • -4 VDDs at 5V • -4 VSSs

  4. Inputs and Outputs Features • Outputs • -1 Output at 5V = Clk_In/2 • -1 Output at 5 V = Clk_In/3

  5. Key Specifications • Skew DIV2-DIV3 < 1ns • Symmetric Tr and Tf DIV2 < 800 ps • Symmetric Tr and Tf DIV3 < 800 ps • Duty Cycle : 45%-55% • Output Load : 10pF

  6. Top Level View of Schematic

  7. Layout View

  8. Extracted View of Layout

  9. Divider Block

  10. Divide by 2 Block

  11. DFF Schematic

  12. DFF Layout

  13. Divide by 3 Block

  14. Layout Divide by 3

  15. Pulse Stretcher

  16. Test Bench • Test functionality of the circuit • Test the outputs skew • Test Tr and Tf of the outputs • Test the duty cycle • Test the driving capability

  17. Schematic of the test bench

  18. Functionality

  19. Functionality

  20. Outputs Skew

  21. Duty Cycle Divide by 2

  22. Duty Cycle Divide by3

  23. Tr of Divide by2

  24. Tf of Divide by2

  25. Tr of Divide by 3

  26. Tf of Divide by3

  27. Conclusion • Process used for the design is AMI16 • Total area used in the design is 1740.47 mil^2 • The circuit is functional • Skew outputs is about 950 ps • Duty cycles 45%-55% • The circuit is capable of driving 20 pF load • Pavg=1/2 x CL x f x VDD^2 • Pavg=1/2 x 20pf x 100MHz x 25 = 25mW

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