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Reiner Hartenstein University of Kaiserslautern

November 21, 2001, Tampere, Finland. Enabling Technologies for Reconfigurable Computing Part 4: FPGAs: recent developments Wednesday, November 21, 16.00 – 17.30 hrs. Reiner Hartenstein University of Kaiserslautern. Schedule. >> Configware Market. Configware Market FPGA Market

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Reiner Hartenstein University of Kaiserslautern

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  1. November 21, 2001, Tampere, Finland Enabling Technologies for Reconfigurable ComputingPart 4:FPGAs: recent developmentsWednesday, November 21, 16.00 – 17.30 hrs. Reiner Hartenstein University of Kaiserslautern

  2. Schedule 2

  3. >> Configware Market • Configware Market • FPGA Market • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead • Soft CPU • HLLs • Problems to be solved 3

  4. Configware heading for mainstream • Configware market taking off for mainstream • FPGA-based designs more complex, even SoC • No design productivity and quality without good configware libraries (soft IP cores) from various application areas. • Growing no. of independent configware houses (soft IP core vendors) and design services • AllianceCORE & Reference Design Alliance • Currently the top FPGA vendors are the key innovators and meet most configware demand. 4

  5. bleeding edge designs • Infinite amount of gates not yet available on a chip • 3 mio gates (10 mio in 2003 ?) far away from "infinite" • Bleeding edge designs only with sophisticated EDA tools • Excessive optimization needed • Hardware epertise is inevitable for the designer. • improve and simplify the design flow the user • provide rich configware libraries of soft IP cores, • control appl., networking, wireless telecommunication, data communication, embedded and consumer markets. 5

  6. Configware (soft IP Products) • For libraries, creation and reuse of configware • To search for IPs see: List of all available IP • The AllianceCORE program is a cooperation between Xilinx and third-party core developers • The Xilinx Reference Design Alliance Program • The Xilinx University Program • LogiCORE soft IP with LogiCORE PCI Interface. • Consultants 6

  7. EDA as the Key Enabler (major EDA vendors) • Select EDA quality / productivity, not FPGA architectures • EDA often has massive software quality problems • Customer: highest priority EDA center of excellence • collecting EDA expertise and EDA user experience • to assemble best possible tool environments • for optimum support design teams • to cope with interoperability problems • to keep track with the EDA scene as a rapidly moving target • being fabless, FPGA vendors spend most qualified manpower in development of EDA, IP cores, applications , support • Xilinx and Altera are morphing into EDA companies. 7

  8. OS for FPGAs • separate EDA software market, comparable to the compiler / OS market in computers, • Cadence, Mentor, Synopsys just jumped in. • < 5% Xilinx / Altera income from EDA SW • Changing EDA Tools Market • Major configware EDA vendors • Altera • Cadence • Mentor Graphics • Synopsys • Xilinx 8

  9. EDA Software for Xilinx • Full design flow from Cadence, Mentor, & Synopsys • Xilinx Software AllianceEDA Program: • Alliance Series Development System. • Foundation Series Development Systems. • Xilinx Foundation Series ISE (Integrated Synthesis Environment) • free WebPOWERED SW w. WebFitter & WebPACK-ISE • StateCAD XE and HDL Bencher • Foundation Base Express • Foundation ISE Base Express 9

  10. ModelSim Xilinx Edition (ModelSim XE) Forge Compiler Modular Design Chipscope ILA The Xilinx System Generator XPower JBits SDK The Xilinx XtremeDSP Initiative MathWorks / Xilinx Alliance System Generator Wind River / Xilinx alliance Foundation ISE Base Express 10

  11. Altera EDA • Altera was founded in June 1983 • EDA: synthesis, place & route, and, verification • Quartus II: APEX, Excalibur, Mercury, FLEX 6000 families • MAX+PLUS II: FLEX, ACEX & MAX families • Flow with Quartus II: Mentor Graphics, Synopsys, Synplicity deliver a design design software to support Altera SOPC solutions. • Mentor: only EDA vendor w. complete design environment f. APEX II incl. IP, design capture, simulation, synthesis, and h/s co-verification • Configware: Altera offers over a hundred IP cores • Third party IP core design services and consultants 11

  12. Cadence • FPGA Designer: top-down FPGA design system, • high-level mapping, architecture-specific optimization, • Verilog,VHDL, schematic-level design entry. • Verilog, VHDL to Synergy (logic synthesis) and FPGA Designer • FPGAs simulated by themselves using Cadence's Verilog-XL or Leapfrog VHDL simulators and • simulated w. rest of the system design w. Logic Workbench board/system verification env‘ment. • Libraries for the leading FPGA manufacturers. 12

  13. Mentor Graphics • System Design and Verification. • PCB design and analysis: • IC Design and Verification • shifts ASIC design flow to FPGAs (Altera, Xilinx) • by FPGA Advantage with IP support • by ModuleWare, • Xilinx CORE Generator • Altera MegaWizard integration, 13

  14. Synopsys • FPGA Compiler II • Version of ASIC Design Compiler Ultra • Block Level Incremental Synthesis (BLIS) • ASIC <-> FPGA migration • Actel, Altera, Atmel, Cypress, Lattice, Lucent, Quicklogic, Triscend, Xilinx 14

  15. >> FPGA Market • Configware Market • FPGA Market • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead • Soft CPU • HLLs • Problems to be solved 15

  16. Actel Xilinx Lattice 6% 42% 15% Altera $3.7 Bio Top 4 PLD Manufacturers 2000 37% Top 4 PLD Manufacturers 2000 16

  17. 1999 rank global sales (mio $) 1998 1999 1 Xilinx 629 899 2 Altera 654 837 3 Lattice 206 410 4 Actel 154 172 5 Lucent 100 120 6 Cypress 41 43 7 Quicklogic 30 40 8 Atmel 32 38 FPGA market 1998 / 1999 Source: IC Insights Inc. Meanwhile, Xilinx acquired Philips' MOS PLD business, Lattice purchased Vantis. . 17

  18. .... into every application • [Dataquest] PLD market > $7 billion by 2003. • „ fastest growing segment of semiconductor market.“ • IP reuse and "pre-fabricated" components for the efficiency of design and use for PLDs • FPGAs are going into every type of application. 18

  19. .... going into every type of application[Gordon Bell] 19

  20. Xilinx • fabless FPGA semi vendor, San Jose, Ca, founded 1984 • key patents on FPGAs (expiring in a few years) • Fortune 2001: No. 14 Best Company to work for in (intel: no. 42, hp no. 64, TI no. 65). • DARPA grant (Nov‘99) to develop Jbits API tools for internet reconfigurable / upgradable logic (w. VT) • Less brilliant early/mid 90ies (president Curt Wozniak): 1995 market share from 84% down to 62% [Dataquest] • As designs get larger, Xilinx losed its advantage (bugfixes did not require to burn new chips) • meanwhile, weeks of expensive debug time needed 20

  21. Xilinx Flexware • Virtex, Virtex-II, first w. 1 mio system gates. • Virtex-E series > 3 mio system gates. • Virtex-EM on a copper process & addit. on chip memory f. network switch appl. • The Virtex XCV3200E > 3 million gates, 0.15-micron technology, • Spartan, Spartan-XL, Spartan-II • for low-cost, high volume applications as ASIC replacements • Multiple I/O standards, on-chip block RAM, digital delay lock loops • eliminate phase lock loops, FIFOs, I/O xlators , system bus drivers • XC4000XV, XC4000XL/XLA, CPLD: low-cost families • rapid development, longer system life, robust field upgradability • support In-System Programming (ISP), in-board debugging, • test during manufacturing, field upgrades, full JTAG compliant interface • CoolRunner: low power, high speed/density, standby mode. • Military & Aerospace: QPRO high-reliability QML certified • Configuration Storage Devices 21

  22. Altera Flexware • Newer families: APEX 20KE, APEX 20KC, APEX II, MAX 7000B, ACEX 1K, Excalibur, Mercury families. • Apex EP20K1500E (0.18-µ), up to 2.4 mio system gates, • APEX II (all-copper 0.13-µ) f. data path applications, supports many I/O standards. 1-Gbps True-LVDS performance • wQ2001, an ARM-based Excalibur device • Altera mainstream: MAX 7000A, 3000A; FLEX 6000, 10KA, 10KE; APEX 20K families. • Mature and other : Classic, MAX 7000, 7000S, 9000; FLEX 8000, 10K families. 22

  23. Configurable system logic ARM Digital Filter Display Interface Viterbi A/D Interface CSI Socket Configurable System Interconnect (CSI) Bus Memory Other System Resources Triscend CSoC [Kean] 23

  24. >> Embedded Systems (Co-Design) • Configware Market • FPGA Market • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead • Soft CPU • HLLs • Problems to be solved 24

  25. HLL Compiler Netlister Place and Route Schematics/ HDL Netlist Bitstream Goal: away from complex design flow [à la S. Guccione] 25

  26. Place and Route . . Schematics/ HDL Netlister Netlist Bitstream Compiler HLL User Code Compiler Executable Overcome traditional separate design flow [à la S. Guccione] 26

  27. Place and Route . . JBits API Schematics/ HDL Netlister Netlist Bitstream Java Compiler User Java Code Executable User Code Compiler Executable Overcome traditional co-processing design separate flow -> JBits Design Flow [à la S. Guccione] 27

  28. FPGA core Compiler HLL Memory core CPU core Compiler HLL Embedded hardw. CPU & memory cores on chip. [à la S. Guccione] 28

  29. new directions in application development • new directions in application development. • aut. partitioning compilers: designer productivity • like CoDe-X (Jürgen Becker, Univ. of Karlsruhe), • supports Run-Time Reconfiguration (RTR), a key enabler of error handling and fault correction by partial re-routing the FPGA at run time, as well as remote patching for upgrading, remote debugging, and remote repair by reconfiguration - even over the internet. 29

  30. >> Run-Time Reconfiguration (RTR) • Configware Market • FPGA Market • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead • Soft CPU • HLLs • Problems to be solved 30

  31. Compiler HLL CPU use for configuration management • on-board microprocessor CPU is available anyhow - even along with a little RTOS • use this CPU for configuration management RTR System Design 31

  32. FPGA core Memory core CPU core HLL Compiler Compiler HLL RTR System Design hard CPU & memory core on same chip 32

  33. JBits API Java Compiler User Java Code Executable Converging factors for RTR • Converging factors make RTR based system design viable • 1) million gate FPGA devices and co-processing with standard microprocessors are commonplace • direct implementation of complex algorithms in FPGAs. • This alone has already revolutionized FPGA design. • 2) new tools like Xilinx Jbits software tool suite directly support coprocessing and RTR. 33

  34. RTR • divides application into a series of sequentially executed stages, each implemented as a separate execution module. • Partial RTR partitions these stages into finer-grain sub-modules to be swapped in as needed. • Without RTR, all conf. platforms just ASIC emulators. • needs a new kind of application development environments. • directly support development and debugging of RTR appl. • essential for the advancement of configurable computing • will also heavily influence the future system organization • Xilinx, VT, BYU work on run-time kernels, run-time support, RTR debugging tools and other associated tools. • smaller, faster circuits, simplified hardware interfacing, fewer IOBs; smaller, cheaper packages, simplified software interfaces. 34

  35. Run-time Mapping • run-time reconfigurable are: Xilinx VIRTEX FPGA family • RAs being part of Chameleon CS2000 series systems • Using such devices changes many of the basic assumptions in the HW/SW co-design process: • host/RL interaction is dynamic, needs a tiny OS like eBIOS, also to organize RL reconfiguration under host control • typical goal is minimization of reconfiguration latency (especially important in communication processors), to hide configuration loading latency, and, • Scheduling to find ’best’ schedule for eBIOS calls (C~side). 35

  36. >> Rapid Prototyping & ASIC Emulation • Configware Market • FPGA Market • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead • Soft CPU • HLLs • Problems to be solved 36

  37. ASIC emulation: a new business model ? • ASIC emulation / Rapid Prototyping: to replace simulation • Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor) • from rack to board to chip (from other vendors, e. g. Virtex and VirtexE family (emulate up to 3 million gates) • Easy configuration using SmartMedia FLASH cards • ASIC emulators will become obsolete within years • By RTR: in-circuit execution debugging instead of emulation 37

  38. >> Evolvable Hardware (EH) • Configware Market • FPGA Market • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead • Soft CPU • HLLs • Problems to be solved 38

  39. EH, EM, ... • "Evolvable Hardware" (EH), "Evolutionary Methods" (EM), „digital DANN“, "Darwinistic Methods", and biologically inspired electronic systems • new research area, also a new application area of FPGAs • revival of cybernetics or bionics: stimulated by technology • „evolutionary“ and „DNA“ metaphor create awareness • EM sucks, also thru mushrooming funds in the EU, in Japan, Korea, and the USA • EM-related international conference series are in their stormy visionary phase, like EH, ICES, EuroGP, GP, CEC, GECCO, EvoWorkshops, MAPLD, ICGA 39

  40. EH, EM, ... • Shake-out phenomena expected, like in the past with „Artificial Intelligence“ • should be considered as a specialized EDA scene, focusing on theoretical issues. • Genetic algorithms suck - often replacable by more efficient ones from EDA • It is recommendable to set-up an interwoven competence in both scenes, EM scene and the highly commercialized EDA scene • EH should be done by EDA people, rather than EM freaks. 40

  41. >> Academic Expertise • Configware Market • FPGA Market • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead • Soft CPU • HLLs • Problems to be solved 41

  42. BRASS (1) • UC Berkeley, the BRASS group: Prof. Dr. John Wawrzynek • The Pleiades Project, Prof. Jan Rabaey, ultra-low power high-performance multimedia computing through reconfiguration of heterogeneous system modules, reducing energy by overhead elimination, programmability at just right granularity, parallellism, pipelining, dynamic voltage scaling. • Garp integrates processor and FPGA; dev. in parallel w. compiler - software compile techniques (VLIW SW pipelining): simple pipelining schema f. broad class of loops. • SCORE, a stream-based computation model - a unifying computational model. Fast Mapping for Datapaths: by a tree-parsing compiler tool for datapath module mapping 42

  43. BRASS (2) • HSRA. new FPGA (& related tools) supports pipelining, w. retiming capable CLB architecture, implemented in a 0.4um DRAM process supporting 250MHz operation • OOCG. Object Oriented Circuit-Generators in Java • MESCAL (GSRC), the goal is: to provide a programmer's model and software development environment for efficient implementation of an interesting set of applications onto a family of fully-programmable architectures / microarchitectures. 43

  44. Berkeley claiming (1) • SCORE, a stream-based computation model: the BRASS group claims having solved the problem of primary impediment to wide-spread reconfigurable computing, by a unifying computational model. • Remark: clean stream-based model introduced ~1980: Systolic Array • 1995: Rainer Kress. Introduces reconfigurable stream-based model • Fast Mapping for Datapaths (SCORE): BRASS claims having introduced 1998 the first tree-parsing compiler tool for datapath module mapping ." Further, it is the first work to integrate simultaneous placement with module mapping in a way that preserves linear time complexity." 44

  45. Berkeley claiming (2) • Remark: The DPSS (Data Path Synthesis System) using tree covering simultanous datapath placement and routing has been published in 1995 by Rainer Kress • „Chip-in-a-Da2 Bee Project. Prof. Dr. Bob Broderson‘s „radical rethink of the ASIC design flow aimed at shortening design time, relying on stream-based DPU arrays.“ [published in 2000] • Remark: the KressArray, a scalable rDPU array [1995] is stream-based 45

  46. .... Stream Processors -MSP-3 • 3rd Workshop on Media and Stream Processors (MSP-3) • http://www.pdcl.eng.wayne.edu/msp01 • in conj. w. 34th Int‘l Symp. on Microarchitecture (MICRO-34) • http://www.microarch.org/micro34 • Austin, Texas, December 1-2, 2001 • Topics of interest include, but are not limited to: • Hardware/Compiler techniques for improving memory performance of media and stream-based processing • Application-specific hardware architectures for graphics, video, audio, communications, and other media and streaming applications • System-on-a-chip architectures for media & stream processors • Hardware/Software Co-Design of media and stream processors • and others .... 46 http://www.microarch.org/micro34

  47. Berkeley: „Chip-in-a-Day“ Bee Project • Chip-in-a-Day Project. Prof. Dr. Bob Broderson, BWRD: targeting a radical rethink of the ASIC design flow aimed at shortening design time. Relying on stream-based DPU arrays (not rDPU and related EDA tools. Davis: „ „... 50x decrease in power requ. over typical TI C64X design.“ • New design flow to break up the highly iterative EDA process, allowing designers to spend more time defining the device and far less time implementing it in silicon. „... developers to start by creating data flow graphs rather than C code,„ • It is stream-based computing by DPU array (hardwired DPA) • For hardwired and reconfigurable DPU array and rDPU array 47

  48. Stanford thru BYU • Stanford: Prof. Flynn went emeritus, Oskar Menzer moved to Bell Labs. • no activities seen other than YAFA (yet another FPGA application) • UCLA: Prof. Jason Cong, expert on FPGA architectures and R& P algorithms. 9 projects, mult. sponsors under California MICRO Program • Prof. Majid Sarrafzadeh directs the SPS project: "versatile IPs„, a new routing architecture, architecture-aware CAD, IP-aware SPS compiler • USC: Prof. Viktor Prasanna (EE dept.) works 20% on reconfigurable computing: MAARC project, DRIVE project and Efficient Self-Reconfiguration. - Prof. Dubois: RPM Project, FPGA-based emulation of scalable multiprocessors. • DEFACTO proj.: compilation - architecture-independent at all levels • MIT. MATRIX web pages removed `99. „RAW project“: a conglomerate • VT. Prof. Athanas: Jbits API f. internet RTR logic ($2.7 mio DARPA). w. Prof. Brad Hutchings, BYU on programming approaches for RTR Systems • BYU. Prof. Brad Hutchings works on the JHDL (JAVA Hardware Description Language) and compilation of JHDL sources into FPGAs. 48

  49. Toronto thru Karlsruhe • U. Toronto. Prof. J.Rose, expert in FPGA architectures and R & P alg. • The group has dev. Transmogrifier C, a C compiler creating netlist for Xilinx XC4000 and Altera's Flex 8000 and Flex 10000 series FPGAs. • Founder of Right Track CAD Corporation acquired by Altera in 1999 • Los Alamos National Laboratory, Los Alamos, New Mexico (Jeff Arnold) – Project Streams-C: programming FPGAs from C sources. • Katholic University of Leuven, and IMEC: Prof. Rudy Lauwereins, methods for MPEG-4 like multimedia applications on dynamically reconfigurable platforms, & on reconf. instruction set processors. • University of Karlsruhe. Prof. Dr.-Ing. Juergen Becker: hardware/software co-design, reconfigurable architectures & rel. synthesis for future mobile communication systems & synthesis w. • distributed internet-based CAD methods, partitioning co-compilers 49

  50. >> ASICs dead ? • Configware Market • FPGA Market • Embedded Systems (Co-Design) • Hardwired IP Cores on Board • Run-Time Reconfiguration (RTR) • Rapid Prototyping & ASIC Emulation • Evolvable Hardware (EH) • Academic Expertise • ASICs dead ? • Soft CPU • HLLs • Problems to be solved 50

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