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Dive into various 3D applications and designs, including chip-level, transistor-level, and wafer-level stacking approaches like TFT and vertical circuits. Compare competitors, discuss density gain, cost impact, speed gain, and reliability. Understand wafer-level stacking approaches by leading companies like Infineon/IBM, Tezzaron, RPI/Ziptronix/ZyCube, focusing on bonding techniques and key challenges. Learn about the objective of reducing gate dimensions and the importance of interconnect delays in chip improvements. Discover how 3D stacking technology can lead to denser, faster, and more efficient electronic devices.
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FaStack Technology A Look at Various 3D Applications, Their Designs, and Ultimate Silicon Results
3D Stacking Approaches Chip Level Transistor Level Wafer Level Matrix: Vertical TFT • Competitors : Conceptual • Infineon/IBM • RPI • Ziptronix • ZyCube • TruSi • Xan3D/Vertical Circuit/Tessera Amkor : 4S CSP (MCP) Tezzaron: Actual Irvine Sensors : Stacked Flash Tezzaron: 3 wafer stack : “Limited” only for PROM : “Expensive” due to low yield : “Extremely slow” : “No” : “No” : “Yes” : “Cost effective” : “Extremely fast” : “yes” : “yes” Density gain : “Yes” Cost impact: “Expensive” Speed gain: “Zero or Negative” Reliability: “No” Multi-Func: “Limited”
Wafer Level Stacking Approaches Infineon/IBM Tezzaron RPI/ Ziptronix/ ZyCube Infineon : W deep via RPI : Dielectric bonding Tezzaron : Copper bonding Ziptronix : Covalent bond (4-inch) Backside of the stacked wafer IBM : SOI wafer thinning ZyCube : Injection glue bonding 3 wafer stack 3D Sensor “All key elements; Alignment, Bonding (Uniformity & Strength), Low thermal budget ( <400C), Si thinning (Control & Uniformity), Limiting stacking yield losses, Facile heat dissipation of wafer level stacking have been simultaneously integrated to meet market demand for density, cost and speed” • Impediments: • Sliced wafer handling • Alignment budget • Uniform bonding • Film stress during deep via fills • Wafer warp • Heat dissipation • Impediments: • Large alignment errors • Strength/uniform bonding, voids • Peeling propensity during thinning • Film stress during deep via fills • Wafer warp • Heat dissipation
“It is clearly seen in Figure 1, that without further reductions in interconnect delay, reducing gate dimensions much below 130nm do not result in corresponding chip improvements.” NSA Tech Trends Q3 2003
Faster!Shorter Wires td 0.35 x rcl2 Propagation delay is proportional to: 1 # of layers
Global Interconnect “problem” • Span of Control
Lower Power! Poweravg = Capacitancetot x Voltage2 x Frequency Therefore: Poweravg Capacitancetot Capacitance is mostly due to wires. Stacked wire length 1 # of layers Therefore: Poweravgstacked Poweravgsingle layer # of layers
Lower Costs! • Less processing per layer • Better optimization per wafer • Higher bit density (memories) • Lower test cost (using Bi-STAR™) • Higher yield (using Bi-STAR™)
