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BE/BI Technical board on Electronics choices for Fast (BLM) electronics. Ewald Effinger, Bernd Dehning 20.03.2014. Outline. Detector overview Diamond Detector with Cascade Schemes (Cividec detector with copper cable) Optical diamond detector from CMS & DESY (BCM1F4LHC)
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BE/BI Technical board onElectronics choices for Fast (BLM) electronics Ewald Effinger, Bernd Dehning 20.03.2014
Outline • Detector overview • Diamond Detector with Cascade Schemes (Cividec detector with copper cable) • Optical diamond detector from CMS & DESY (BCM1F4LHC) • BLMED Installation Overview • Motivation for a new Fast DAQ • Technical Specification of Fast DAQ • System propositions • Solution CERN made or outside company • FMC based system (BI development) • Tender System 1 – System 5 • System Compare
New Diamond Detector Cascade Schemes • Detector signal split in two signal paths (direct and 40dB amplified) • Monitoring of complete dynamic range possible • No need to access tunnel to exchange amplifier for different users
Optical diamond detector (BCM1F4LHC) • All detector signal arrive on the same position • Easy access of data acquisition system • Lower dynamic range
BLMED Installation Overview • Following detectors are foreseen to be installed while LS1 and LS2 • 1 detector for Fast Servospill in the SPS TT20 (LS1) • 1 detector for HiLumi in the LHC (LS1) • 8 detectors for Booster dump (LS2) • 12 (?) detectors for PS (LS2)
Motivation for a new Fast DAQ • More reliability of data acquisition in compare with windows based LeCroy Scope • Decrease rental cost for scopes • (450CHF per month and scope) • Less complicated set up for BCM1F detector • Supported and maintained by DESY • Complex data treatment structure • Single data acquisition system for both detector types • Equal readout and data treatment for both detectors
System propositions • 8 - 10 - 12 bit solution possible • 3 – 4 channel per system needed • Splitter and/or optical input • can be separated form DAQ • In case of a modular system more than 4 channel possible • Parallel processing of Histogram and Loss versus time mode preferable
FMC based system (BI development) • System based on BI VFC board • Digitizer FMC board, 8/10/12 ADC 1GSPS, no memory on the board. • VME 64 create and Linux CPU needed per system • Not compatible with dead lines of project • Series production of VFC (start end of 2014) • Tender for FMC card • FPGA and CPU Software form BI needed
Tender System 1 • Custom made MTCA 4 Channel 1.25GSPS 10bit ADC • Virtex 6 FPAG and DDR3 memory interface • FPGA software done by vendor • Create and single board computer and MCH not included (not included in the offer) • Offer not compatible with dead line • CPU software not mentioned
Tender System 2 • 3 * 1 Channel 1.6GSPS 12bit ADC • FPGA board with Kintex -7 and 2 Gbit RAM • 2.3 GHz Quad-Core PXI Express Controller • 8-Slot 3U PXI Express Chassis with AC - Up to 7 GB/s • Modular system, stand alone • Compatible with dead line • CPU and FPGA Software consulted by vendor
Tender System 3 • 1 * 4 Channel 1.25 GSPS 8bit ADC with Xilinx Virtex 5, 16 GB compact flash card • 1 * 2 Channel 2.5 GSPS 8 bit ADC with Xilinx Virtex 5 • Mother board NANO-PV-D5251with Intel Atom D525 1.8 GHz and 4GB RAM, Linux based software. • 5 Gbit/s connection between ADC and CPU . • Compatible with dead lines • CPU and FPGA Software included in the offer
Tender System 4 • No specified description given in the offer • New custom made development all requirements should be fulfilled • Compatible with dead lines
Tender System 5 • 1 * 4 Channel 1GSPS 12bit ADC with Virtex 6 and 1 Gbit RAM • Analogue frontend with selectable gain • Linux based CPU to connected to ADC and data treatment. • 19 “ chassis, stand alone system • CPU and FPGA Software included in the offer
System Compare Values in grey correspond to specified values !