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Digital Double Column & End of Column status, verification, and simulation results

Digital Double Column & End of Column status, verification, and simulation results . Tomasz Hemperek. Pixel Digital Region - Functionalities. Pixel Digital Region - Layout. 190  m. 100  m. Region Parameters (4 pixels). Area 102x100 um (ARM Cells) Buffer Overflow Inefficiency

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Digital Double Column & End of Column status, verification, and simulation results

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  1. Digital Double Column & End of Column status, verification, and simulation results Tomasz Hemperek

  2. Pixel Digital Region - Functionalities

  3. Pixel Digital Region - Layout 190m 100m

  4. Region Parameters (4 pixels) • Area • 102x100 um (ARM Cells) • Buffer Overflow Inefficiency • about 0. 05 % for 3xLHC • about 2.20% for 10xLHC • Power consumption (average) with parasitics(ETS) • ~12 uW/region (~3uW/pixel)- 1hit/BC/DC, 100kHz trigger

  5. Array Organization • Two token scenario (column and periphery level) • One data bus (token type) • End of column logic selects column to read • Chip control logic controls trigger and read • Pixels are always read in the same order

  6. Digital Double Column • Signal Distribution • Clock Distribution

  7. Digital Double Column – yield • Possibility to turn off digital region (in and out) • Triplicated Token with majority voting in every region • Hamming protection code on data bus • Hamming protected row address with thermal decoder

  8. Digital Double Column - layout BUFFERS

  9. Digital Double Column – average power • Parasitic extraction with QRC • Results for Double-Column (2x336 pixels) • Activity : 1hit/25ns/DC, 100kHz trigger • Tools: PrimeTime clock network (TT): 3.721 mW 2 hits/25ns/DC (TT): 5.290 mW

  10. Digital Double Column – analog simulation • 4 region (16 pixels) post-layout simulation (QRC+HSIM) no decupling

  11. End of Column Logic • Column token management • Controls the read of column • Distribute signals to DDC • Triple redundant logic • Hamming protected data • Stop clock enable Logic Layout ready and simulated

  12. Summary • All blocks ready and verified (post layout) • Need integration with other analog and digital blocks • Need some mixed-signal verification

  13. BACKUP SLIDES

  14. Hit processing (HC3 mode)- schematic • Receives comparator output • BC resolution • Generates Leading Edge (LE) • Generates Small hit Leading Edge (sLE) • Generates Trailing Edge (TE) • Generates ToT counter reset and enable (rst_cnt, en_cnt) 14

  15. ToT processing - schematic • Start ToT Counter • Global LE generation (orLE) • Reset memory signal generation (rst_mem) • Memory pointer selection (freeAddr) • Record reset/small in memory • Record neighbor • Record TOT value in memory 15

  16. Memory Management - schematic • Selects free memory • Token management • Selects triggered memory during read • Enables outputs Design: x5 latency cell 16

  17. Latency Memory/Trigger- schematic • Start/Reset latency counter • Indicate status (full) • Trigger (triggered) • Store/Recognize trigger ID 17

  18. Buffer overflow inefficiency • Physical data from Genova • Buffer overflow inefficiency in [%] 18

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