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PROCESSOR POWER SAVING ~CLOCK GATING~

PROCESSOR POWER SAVING ~CLOCK GATING~. Kautalya Mishra. CLOCK. MULTI-CYCLE DATAPATH. CTR. MOTIVATION. Unnecessary power is consumed by components that are not currently in use in an instruction cycle. This power can be reduced by appropriately turning off clocks that feed into them.

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PROCESSOR POWER SAVING ~CLOCK GATING~

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  1. PROCESSOR POWER SAVING~CLOCK GATING~ Kautalya Mishra

  2. CLOCK MULTI-CYCLE DATAPATH CTR

  3. MOTIVATION Unnecessary power is consumed by components that are not currently in use in an instruction cycle. This power can be reduced by appropriately turning off clocks that feed into them. Ideally we would expect a good amount of power saving in all the components being clocked and also in the combinational elements the registers are feeding into.

  4. CLOCK-GATING CTRL CLKout CLOCK COMPONENTS CLOCK-GATED • MEMORY • REGISTER FILE • MEMORY DATA REGISTER • INSTRUCTION REGISTER • PC REGISTER • ALUOUT REGISTER • 16 BIT REGISTERS

  5. STEPS CODE THE DATAPATH, CONTROL UNIT AND THE MEMORY IN VHDL CONVERT THE VHDL FILE TO A VERILOG FORMAT USING LEONARDO SPECTRUM ~ TECHNOLOGY 180 nm CONVERT THE VERILOG GATE LEVEL NET LIST TO A RUTGURS MODE FORMAT USING THE POWERSIM TOOL GENERATED A GATE LEVEL NETLIST IN DESIGN ARCHITECT ESTIMATE POWER CONSUMED BY THE PROCESSOR WITH AND WITH CLOCK-GATING AND EVALUATE POWER SAVING

  6. VHDL MODELS WITHOUT CLOCK-GATING WITH CLOCK-GATING REGISTER REGISTER DATA OUT DATA OUT DATA IN DATA IN CLOCK CTR CLOCK

  7. POWER ESTIMATION • Started off by attempting to estimate power consumed by the processor as a whole using the POWERSIM tool but no results were obtained because of a segmentation fault. • Estimated power consumed by each component feeding in appropriate (not random!) input vectors that would have flown through in the datapath otherwise. • Output loading of an individual component is not considered

  8. RESULTS The leakage losses in some components can be expected as the component is in an off state longer. Some components show high leakage losses (like -75%) but that is only because of the small values of the leakage power. --Power estimation done over the first 10 input vectors--

  9. TOTAL POWER SAVING

  10. POWER SAVING IN regMDR

  11. CONCLUSION Clock-gating is a very neat way of reducing power consumed in a processor. Its authenticity however would have to be verified over longer clock cycles and for varying technologies.

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