ON THE INTERACTION BETWEEN POWER-AWARE FPGA CAD ALGORITHMS

JulienLamoureux and Steven J.E Wilton ICCAD 2003 ON THE INTERACTION BETWEEN POWER-AWARE FPGA CAD ALGORITHMS

Outline • Introduction • Algorithms • Experimental results • Conclusion

Introduction Circuit F PGA CAD FLOW Technology Mapping(CutMap) Clustering(T-VPack) Placement(VPR:T-VPlace) Routing(VPR Router) Delay / Area / Power Estimations

f1 A B f2 C D E f3 F 0 x 0 1 y ... ... ... z 1 0 SRAM f Introduction A mapping Technology mapping transforms a netlistof gatesandregistersinto a netlist of K-input lookup tables (K-LUTs) and registers. B C D E

Figure 1: An N cluster Figure 2: A LUT and flip-flop BLE Introduction

ABC f1 f3 f1 D E F f2 f2 f3 Introduction A B C D E F Mapping + Clustering Placement Routing

Algorithms Circuit F PGA CAD FLOW Technology Mapping(EMap) Clustering(P-T-VPack) Placement(P-T-VPlace) Routing(P-VPR Router) Delay / Area / Power Estimations

Technology Mapping

Clustering Crit(B) is a measure of how close LUT B is to being on the critical path, Nets(B) is the set of nets connected to LUT B, Nets(C) is the set of nets connected to the LUTs already selected for cluster C • T-VPack • P-T-VPack Activity(i) is the estimated switching activity of net i, Activityavgis the average switching activity of all the nets in the user circuit.

Clustering

Algorithms Circuit F PGA CAD FLOW Technology Mapping(EMap) Clustering(P-T-VPack) Placement(P-V-Place) Routing(P-VPR Router) Delay / Area / Power Estimations

q(i) is used to scale the bounding boxes to better estimate wirelength for nets with more than 3 terminals, as described in [9]. Delay(i,j) is the estimated delay of the connection from source i to sink j, CE is a constant, and Criticality(i,j) is an indication of how close to the critical path the connection is [9]. bbx(i) and bby(i) are the x and y dimensions of the bounding box of net i Placement • T-Vplace • P-T-VPlace

Placement

Routing The baseline VPR router uses the following cost function to evaluate a routing track n while forming a connection from source i to sink j: b(n) is the “base cost”, h(n) is the historical congestion cost, and p(n) is the present congestion of node n. • VPR-Router • P-VPR-Router Activity(i) is the switching activity in net i, MaxActivity is the maximum switching activity of all the nets, andMaxActCritis the maximum activity criticality that any net can have. cap(n) is the capacitance associated with routing resource node n and ActCrit(i) is the activity criticality of net i.

Routing

Experimental results

Node Duplication • 3-LUTs mappings: With duplication No duplication

ON THE INTERACTION BETWEEN POWER-AWARE FPGA CAD ALGORITHMS

ON THE INTERACTION BETWEEN POWER-AWARE FPGA CAD ALGORITHMS

Presentation Transcript

Power-aware scheduling

Ethernet on the FPGA

Interaction Between the Sexes

FPGA Technology Mapping Algorithms

Decoding-Aware Compression of FPGA Bitstream

Interaction Between the Sexes

Power-Aware FPGA Logic Synthesis Using Binary Decision Diagrams

Power Aware Computing

FPGA CAD

FPGA Implementation of Lookup Algorithms

CAD Algorithms and Tools

FPGA Technology Mapping Algorithms

Power-Aware Placement

Power-aware RAM Processing for FPGA Embedded Memory Blocks

Communication Between FPGA and LabView - FPGA part

Power Aware Synthesis

PADS Power Aware Distributed Systems Algorithms

Interaction between organisms

Power-Aware Architecture

Power-Aware Placement

Power-Aware Microprocessors

Power-aware scheduling