CAD Algorithms and Tools

1. CAD Algorithms and Tools

2. Overview • Introduction • Multi-level logic synthesis • SIS as a representative CAD tool • Boolean networks • Transformations of Boolean networks • sweep, eliminate, fast_extract, resub, full_simplify • Optimization loop • Implementation • network/node data structure, packages, scripts • Conclusions • Software demo

3. Introduction • Multi-level logic synthesis • Description, motivation, results • Logic synthesis methods • In the past, applied by hand; now, by the tools • CAD tools • Experimental, industrial

4. SIS • The first comprehensive open-source logic synthesis tool • Based on a decade of research at UC Berkeley and other universities (1983-1993) • Precursor of many modern CAD tools • Gives a good idea what is inside those tools • Source code, benchmarks available on-line: http://www-cad.eecs.berkeley.edu/Software/software.html

5. Boolean Networks • Boolean network is a direct acyclic graph Primary outputs (POs) Primary inputs (PIs) Internal nodes

6. Fanin/Fanout of a Node • Node has only one output. • Node can have any number of inputs (fanins) • and can be an input to any number of nodes (fanouts) FO3 FO1 FO2 Fanouts N Node FI2 FI3 FI1 Fanins

7. Transitive Fanin/Fanout of a Node Transitive fanout Transitive fanin N

8. Optimizing Transformations on Boolean Networks Factoring F = a’c + a’d + bc + bd + e  F = (a’+b)(c+d) + e

9. Common logic extraction F = (a + b)cd + e F = XY + e G = (a + b)e’  G = Xe’ H = cde H = Ye X = a + b Y = cd H F G G H F X Y

10. Resubstitution G = a + b + c G = a + b + c F = a + bd + cd  F = G(a+d) F F G G

11. Elimination G = a + b + c G = a + b + c F = G(a+d)  F = a + bd + cd F F G G

12. Sweep • Removes nodes that do not fanout • Eliminates constant nodes and single-input nodes (buffers, inverters)

13. full_simplify • Simplifies each node in the network using don’t-cares

14. Don’t-cares for Nodes in the Network • External don’t-cares • Some input combinations never occur (unused codes, unreachable states) • Internal don’t-cares • Satisfiability don’t-cares • Some input combinations never occur at a node • Observability don’t-cares • Under some input combinations, the value produced at the output of the node does not matter

15. Satisfiability Don’t-cares • (x,y)=(1,0) is a don’t-care for node F x a z1 F b y c

16. Observability Don’t-Cares • (a,c)=(1,1) is a don’t-care for node F a z1 F b z2 c

17. Role of sophisticated representations, data structures and algorithms. node_struct Structure of a node struct node_struct { char *name; /* name of the output signal */ char *short_name; /* short name for interactive use */ node_type_t type; /* type of the node */ int sis_id; /* unique id (used to sort fanin) */ unsigned fanin_changed:1; /* flag to catch fanin generation errors */ unsigned fanout_changed:1; /* flag to catch fanout generation errors */ unsigned is_dup_free:1; /* node has no aliasing of its fanin */ unsigned is_min_base:1; /* node is minimum base */ unsigned is_scc_minimal:1; /* node is scc-minimal */

18. node_struct (continued) int nin; /* number of inputs */ node_t **fanin; /* the array of pointers to the input nodes */ lsList fanout; /* list of 'fanout_t' structures */ lsHandle *fanin_fanout; /* handles of our fanin's fanout_t structure */ pset_family F; /* on-set */ pset_family D; /* dc-set -- currently unused */ pset_family R; /* off-set */ node_t *copy; /* used by network_dup(), network_append() */ network_t *network; /* network this node belongs to */ lsHandle net_handle; /* handle inside of network nodelist */ };

19. Structure of a network network_struct struct network_struct { char *net_name; /* the name of the network */ st_table *name_table; /* table to hash names into node pointers */ st_table *short_name_table; /* table to hash names into node pointers */ lsList nodes; /* list of all nodes */ lsList pi; /* list of just primary inputs */ lsList po; /* list of just primary outputs */ network_t *dc_network; /* external don't care network */ st_table *latch_table; /* table to hash names into latch pointers */ lsList latch; /* the linked list of latches */ graph_t *stg; /* state transition graph */ char *clock; /* the clock */ char *default_delay; /* stores default delay info */ astg_t *astg; /* asynchronous signal transition graph */ };

20. Role of scripting and user-directed synthesis script.rugged sweep; eliminate -1 simplify -m nocomp eliminate -1 sweep; eliminate 5 simplify -m nocomp resub -a fx resub -a; sweep eliminate -1; sweep full_simplify -m nocomp Scripts to control the synthesis process

21. What’s next? • Multi-valued logic optimization • New CAD tool: MVSIS • Reversible logic synthesis • Quantum, DNA-based, etc

22. full_simplify SIS vs. MVSIS

23. Conclusions • Reviewed multi-level logic optimization • Introduced Boolean networks • Considered typical operations • Looked into the implementation of SIS

24. Problems for students • What are BDDs and how are they used. • Shannon expansion and its role in trees and diagrams • Boolean networks • Operations on Boolean Networks. • Various types of don’t cares and their use • SIS system in practice.

25. Sources Alan Mishchenko Electrical and Computer Engineering Portland State University