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The LCLS Timing & Event System - An Introduction – John Dusatko / Accelerator Controls

The LCLS Timing & Event System - An Introduction – John Dusatko / Accelerator Controls. Outline. Introduction to LCLS Some background on SLAC Timing The SLAC Linac Timing System The LCLS Timing System Issues. Introduction. LCLS Introduction.

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The LCLS Timing & Event System - An Introduction – John Dusatko / Accelerator Controls

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  1. The LCLS Timing & Event System- An Introduction –John Dusatko / Accelerator Controls

  2. Outline • Introduction to LCLS • Some background on SLAC Timing • The SLAC Linac Timing System • The LCLS Timing System • Issues

  3. Introduction

  4. LCLS Introduction • The Linac Coherent Light Source is an X-ray FEL based on the SLAC Linac: • 1.0nC, 14GeV e- are passed thru an undulator, a Self Amplifying Stimulated Emission process produces 1.5 Angstrom X-Rays. • LCLS is an addition to the existing SLAC Linac: it uses the last 1/3 of the machine • This is important to note because we have to integrate the New LCLS Timing System with the Existing Linac (SLC) Timing System.

  5. The LCLS – Schematic View (ignoring photon beamline) Single bunch, 1-nC charge, 1.2-mm slice emittance, 120-Hz repetition rate… 250 MeV z  0.19 mm   1.6 % 4.54 GeV z  0.022 mm   0.71 % 14.1 GeV z  0.022 mm   0.01 % 6 MeV z  0.83 mm   0.05 % 135 MeV z  0.83 mm   0.10 % Linac-X L =0.6 m rf= -160 rf gun Linac-1 L 9 m rf  -25° Linac-2 L 330 m rf  -41° Linac-3 L 550 m rf  -10° new Linac-0 L =6 m undulator L =130 m 21-1b 21-1d 21-3b 24-6d 25-1a 30-8c X ...existing linac BC-1 L 6 m R56 -39 mm BC-2 L 22 m R56 -25 mm DL-1 L 12 m R56 0 LTU L =275 m R56  0 research yard SLAC linac tunnel (RF phase: frf= 0 is at accelerating crest)

  6. LCLS Timing – Some Definitions • The LCLS Timing System can be viewed as consisting of three parts: • Part 1: ‘Standard’ Accelerator Timing • 10ps Triggers for Acceleration and Diagnostics • Part 2: S-Band Timing • 2856MHz LCLS RF Phase Reference Distribution • Part 3: Ultra-Precise Timing • 10fs Synchronization for Experiments (LBL System)

  7. LCLS Timing – Some Definitions • The LCLS Timing System can be viewed as consisting of three levels: • Part 1: ‘Standard’ Accelerator Timing • 10ps Triggers for Acceleration and Diagnostics • ‘Triggers’ are signals from the timing system used by HW to accelerate & measure the beam • Part 2: S-Band Timing • 2865MHz RF Phase Reference Distribution • Part 3: Ultra-Precise Timing • 10fs Synchronization for Experiments (LBL System)

  8. LCLS Timing – Performance Requirements

  9. Requirements Comparison • Timing Reqmts for earlier SLAC systems: Original Linac: (~1968) • Resolution: 50 nSec - Jitter: 15 nSec - Main Trigger Line Waveform: + / - 400 Volts PEP – II: (~1998) - Resolution: 2.1 nSec - Jitter: 20 pSec - NIM Level Waveform: 0 to –0.7 V into 50 Ohms

  10. Background

  11. SLAC’s Timing Systems • In order to explain the New LCLS timing system, we first need to understand how the old SLAC timing system works – i.e. how we got from there to here • The SLAC Accelerator complex consists of several machines: Linac, Damping Rings, Stanford Linear Collider, PEP-II, FFTB, NLCTA / each with its own timing sub-system • The overall timing system consists of incremental add-ons to the original system • Design Challenge for LCLS Timing System was that it had to know about and work with the existing system

  12. (pre-LCLS) SLAC Accelerator Complex(Lots of Pieces)

  13. SLAC Linac Timing System

  14. Old SLAC Timing System We’ll talk a little about the existing SLAC Linac Timing System: • The Linac is a Pulsed Machine (get a packet of beam per pulse) runs at a max of 360Hz • Three Main Timing Signals: • 476MHz Master Accelerator Clock (runs down 2mile Heliax Main Drive Line cable) • 360Hz Fiducial Trigger (used to ‘tell’ devices when the beam bunch is present) / encoded onto the 476MHz master clock • 128-Bit PNET (Pattern Network) Digital Broadcast

  15. Some More Details • Why 360Hz? • Original design rate of the Linac / derived from the 3-phase, 60Hz AC power line frequency: want to trigger devices (Klystrons, etc.) consistently so as to not create huge transients on the Power Line Sync’d to 476MHz • PNET Broadcast • A special computer called the Master Pattern Generator (triggered by the 360Hz fiducial) broadcasts a 128-bit digital message containing information (conditions, rate, charge, etc.) about the beam • This is used by the Trigger Generator computers to set up triggers and their delays • Sent over SLAC coax cable TV network

  16. How The 360Hz is Generated The Sequence Generator creates a 360Hz signal as well as 6 Timeslot pulses (used for further synchronization) Source: SLAC Blue Book c.1962

  17. Timing HW at Head-End of Linac For Phase Stabilization

  18. Generation of The Linac Timing Signal (AM Modulator) • The 360Hz Signal is Amplitude Modulated onto the 476MHz Accelerator Clock and propagated down the Main Drive Line. • The AM process is not ideal and some FM occurs; in addition, the signal gets more dispersed as it heads down the 2 mile MDL

  19. Linac RF Phase Reference Distribution • This slide is to give you an idea of how the Linac Phase Reference is used Each sector (30 total) taps off the MDL, to extract the RF clock This is just the Phase Ref, trigger generation is accomplished by a different set of HW

  20. Trigger Generation Timing CAMAC Crate • Old Timing System (CAMAC based) generates triggers by combining the RF Clock, 360Hz Fiducial and PNET Data • 476MHz is divided/4 to get 119Mhz + fiducial by another system / This is because the older technology HW could not run at 476MHz PNET Data on Serial Link • The Programmable Delay Unit (PDU) Module generates the triggers. It contains digital counters that get set with delay values from PNET and started when the Fiducial Pulse comes along

  21. The LCLS Timing System

  22. Finally – The LCLS Timing System • Old CAMAC System is no longer viable for new Systems (performance limited, obsolete) • Seek to implement a new Timing System that has similar functionality, better performance, and can be laid atop the old system, working alongside it • In addition, LCLS has have its own master oscillator (PLL sync’d with Linac MO) and local phase reference distribution system at S20 • LCLS System is VME based, using High-Speed digital serial links to send Clock, Trigger and Data all on one optical Fiber to timing clients

  23. LCLS RF Front End LCLS Master Osc – slaved to Linac MO / Lower Phase noise req’d by LCLS

  24. LCLS Timing/Event System Architecture Linac main drive line ~ Low Level RF LCLS Timing System components are in RED 476 MHz LCLS Master Oscillator Sync/Div Linac Master Osc 119 MHz 360 Hz System is based around the EVent Generator and EVent Receiver SLC MPG P N E T I O C E V G F A N LCLS events SLC events fiber distribution Precision<10 ps * EPICS Network Digitizer LLRF BPMs Toroids Cameras Wire Scanner SLC klystrons I O C E V R D E V TTL * m P P N E T P D U TTL-NIM convert. SLC Trigs *MicroResearch

  25. The Event System • Based on Commercial Hardware (MicroResearch Finland) • Which was based on a design from ANL-APS Timing System • Designed Around Xilinx Virtex-II FPGAs • Uses FPGA’s internal High-Speed 2.38 Gb/s Serial xcvr, which connects to a fiber optical transceiver • FPGA logic implements all of the timing functions • Uses 119MHz clock from Linac which get multiplied up to by FPGA internal PLL to 2.38GHz • EVG sends out 8-bit event code to EVRs along with clock and trigger information over one fiber • EVR Receives event code & with its associative memory, generates a trigger with a delay set by digital counters

  26. The Event System • Upon RX’ing a 360Hz Fid, the EVG sends out a stream of serial Data to the EVRs over a fiber link. The serial stream consists of 16-bit words sent every 8.4ns. • Each word contains an Event Code byte and some trigger setup data

  27. EVG contains a RAM that gets loaded with event codes, based on PNET data. 360Hz Fiducial causes the RAM to get sent out over the Serial fiber link to the EVRs. Event Generator

  28. Event Receiver • EVR contains another RAM that looks for matches of event codes to its contents. If match, it starts a counter running that generates a trigger

  29. EVG Hardware Event Generator VME-64x Module: Sits in Master Timing Crate with VME PNET receiver and Master Timing CPU. • Receives 119MHz reference and 360Hz master timing fiducial from SLC timing system. • Receives PNET pattern from SLC system. • Broadcasts timing system data in the form of a high-speed 25Gb/s serial data stream to the EVRs over an optical fiber.

  30. EVR Hardware Event Receiver • Comes in two flavors: VME and PMC. • Receives 2.5Gb/s serial datastream from EVR and generates triggers based on values of the event codes. • Also receives and stores PNET timing pattern, EPICS timestamp and other data and stores them in an internal data buffer. • Can output 14 total pulsed-output triggers and several more level-type • Triggers are output via a rear transition module (not shown) • Trigger delay, width, duration and polarity are fully programmable • Trigger signal level format is TTL • VME Version has 10ps jitter • PMC Version has 25ps jitter

  31. System SW

  32. What Happens during one 2.8mS machine interval: Record processing (event, interrupt) Hardware Triggers Receive pattern for 3 pulses ahead Triggering Event Codes Start Beam Kly Standby Event Timestamp, pattern records, and BSA ready Acq Trigger Kly Accel Fiducial Event Received Fiducial B0 F3 18 500 0 1023 100 0.3

  33. Performance • The Event System Trigger Jitter was measured using an Agilent Infinium 54845A Digital Oscilloscope in Jitter Histogram Mode / data was collected for 30 minutes • The EVR output (shown) was measured against the system input trigger (360Hz fiducial) • The Actual jitter performance is much better after subtracting off the intrinsic jitter of the scope: Actual Jitter: JITTERsystem = [ (JITTERsys_meas)2 – (JITTERscope)2 ]1/2 Event System Jitter: JITTEREVR =[ (9.7472ps)2 – (6.3717ps)2 ]1/2 = 7.3763 ps EVR jitter w.r.t. fiducial 9 ps rms jitter

  34. Issues • Current LCLS Timing System has growing pains (integration w/old system, SW, HW) • Use of commercial HW doesn’t quite fit our needs / having to modify EVG & EVR • System scalability / with an eye towards eventually replacing the old SLAC timing system with this one (we think it will work..) • Phase Drift on Fiber (where Russell’s Laser System will help us)

  35. Issues – Fiber Phase Drift Temperature-Dependent Phase Delay The Fiber-Optic cable will experience temperature-induced optical transport and length variations which will affect the timing. What should we expect? Calculation (warning hand-waving guesstimate!): Delay Coefficient: 30ps/C/Km (source J. Frisch ILC timing notes) Worst Case (max length / largest temp variation): Length: Sector 20  FEH (~2.2Km) Temperature Variation: 32F – 100F (0C – 40C) (typ winter/summer)

  36. Temperature-Dependent Phase Delay (cont.) • How will this affect the timing system? • Badly, but its not a 1:1 correlation between the trigger timing and the fiber phase delay • Why? Because the fiber contains a 20-bit serial digital data stream (w/embedded clock) that gets recovered and decoded at the receiver. So its not straightforward to understand the effect • Here’s a guess: • 20-bit datastream @ 2.38Gb/s  1 bit cell = 420ps • With = 2204ps  5 to 6 bit slots get shifted. This will affect when the Event Code gets de-serialized and loaded in the memory to produce a trigger • The trigger could jump around by 8.4ns (119Mhz clk cycle) increments > This is one of the LCLS applications that needs the Stabilized Laser Distribution System

  37. End of Talk

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