1 / 16

FEE Controls

FEE Controls. Main Goals: Define “common language” to describe DCS subsystems for all ALICE subdetectors Identify problematic points Find and implement solutions. Example: ALICE SPD. SPD Elements. Readout Chip. Pilot MCM. Bus. Detector. 2mm. 11mm. SMD component. 7. 7. 7. 6.

galena
Download Presentation

FEE Controls

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Alice DCS Workshop 18-3-2002

  2. FEE Controls • Main Goals: • Define “common language” to describe DCS subsystems for all ALICE subdetectors • Identify problematic points • Find and implement solutions Alice DCS Workshop 18-3-2002

  3. Example: ALICE SPD Alice DCS Workshop 18-3-2002

  4. SPD Elements Readout Chip Pilot MCM Bus Detector 2mm 11mm SMD component 7 7 7 6 235 µm 5 Aluminium 4 3 2 1 Polyimide PIXEL DETECTOR 400 µm READOUT CHIP COOLING TUBE Alice DCS Workshop 18-3-2002

  5. R1 =4 cm R2 =7 cm SPD Layout Alice DCS Workshop 18-3-2002

  6. SPD DCS Architecture Half-stave Voltage Regulators HV LV Alice DCS Workshop 18-3-2002

  7. SPD DCS Architecture PVSS Control + Monitoring Half-stave Voltage Regulators HV LV Alice DCS Workshop 18-3-2002

  8. SPD DCS Architecture PVSS Control + Monitoring Router (VME) DAQ JTAG MCM Data Half-stave Voltage Regulators HV LV Alice DCS Workshop 18-3-2002

  9. SPD DCS Architecture PVSS Control + Monitoring Router (VME) DAQ DCS JTAG MCM Data + SC T I,V Half-stave Voltage Regulators HV LV Alice DCS Workshop 18-3-2002

  10. SPD DCS Architecture PVSS Control + Monitoring Router (VME) DAQ DCS JTAG VR JTAG MCM Data + SC T I,V Half-stave Voltage Regulators HV LV Alice DCS Workshop 18-3-2002

  11. SPD DCS Architecture PVSS Control + Monitoring Router (VME) DAQ DCS JTAG VR JTAG MCM Data + SC T I,V Half-stave Voltage Regulators HV LV Interlock 1 2 Alice DCS Workshop 18-3-2002

  12. SPD DCS Architecture PVSS Control + Monitoring Router (VME) DAQ DCS JTAG VR JTAG MCM Data + SC T I,V Half-stave Voltage Regulators HV LV Interlock 1 2 Alice DCS Workshop 18-3-2002

  13. SPD DCS Architecture PVSS Control + Monitoring Router (VME) DAQ DCS JTAG VR JTAG MCM Data + SC T I,V Half-stave Voltage Regulators HV LV Interlock 1 2 Alice DCS Workshop 18-3-2002

  14. SPD DCS Architecture PVSS Control + Monitoring Router (VME) DAQ DCS JTAG VR JTAG MCM Data + SC T I,V Half-stave Voltage Regulators HV LV Interlock 1 2 Alice DCS Workshop 18-3-2002

  15. Alice 1 Readout channel Pixel Cell Parameters: 3 Local Threshold Adjust Bits 1 Mask Bit 1 Test Bit Readout Chip Parameters: 44 x 8-bit DACs SPD Total: ~ 50.000.000 configuration bits Alice DCS Workshop 18-3-2002

  16. Some Open Questions • Hardware and Software Implementation (eg. JTAG) • Monitoring Strategy • Single event Effects Alice DCS Workshop 18-3-2002

More Related